Visible to Intel only — GUID: ewa1405111963624
Ixiasoft
Visible to Intel only — GUID: ewa1405111963624
Ixiasoft
3.10. FPGA Programming Flow
The default FPGA programming flow is to compare the periphery currently programmed on the FPGA with the periphery of a new design. If they match, programming through CvP replaces the existing FPGA core with the new core. If they differ, programming through external flash memory replaces the existing FPGA periphery with the new design. FPGA programming using quartus_pgm via Intel® FPGA Download Cable is an old approach. Only use this programming method if you use a cable to connect the board and the host computer. Cabling is a point of potential failure, and it does not scale well to large deployments. The quartus_pgm approach remains for development and testing purposes, and for use on boards that do not have an alternative method (such as Flash) for periphery replacement.