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2.1. Initializing Your Custom Platform
2.2. Removing Unused Hardware
2.3. Integrating Your Custom Platform with the Intel® FPGA SDK for OpenCL™
2.4. Setting up the Software Development Environment
2.5. Building the Software in Your Custom Platform
2.6. Establishing Host Communication
2.7. Connecting the Memory
2.8. Integrating an OpenCL Kernel
2.9. Programming Your FPGA Quickly Using CvP
2.10. Guaranteeing Timing Closure
2.11. Troubleshooting
3.1. Host-FPGA Communication over PCIe
3.2. DDR3 as Global Memory for OpenCL Applications
3.3. QDRII as Heterogeneous Memory for OpenCL Applications
3.4. Host Connection to OpenCL Kernels
3.5. Implementation of UDP Cores as OpenCL Channels
3.6. FPGA System Design
3.7. Guaranteed Timing Closure
3.8. Addition of Timing Constraints
3.9. Connection to the Intel® FPGA SDK for OpenCL™
3.10. FPGA Programming Flow
3.11. Host-to-Device MMD Software Implementation
3.12. OpenCL Utilities Implementation
3.13. Stratix V Network Reference Platform Implementation Considerations
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3.6.6. Encrypted IPs
The Stratix® V Network Reference Platform incorporates two encrypted IP cores. They are the PLDA QuickUDP IP and the CPLD_bridge IP. The CPLD_bridge IP enables communication between the FPGA and external CPLD.
Incorporation of these IP cores in s5_net demonstrates that it is feasible to use the Intel® FPGA encryption infrastructure to encrypt IPs within a Custom Platform.
Contact your field application engineer for more information on how to encrypt IP for use with the Intel® Quartus® Prime software.