Intel® FPGA SDK for OpenCL™: Stratix® V Network Reference Platform Porting Guide

ID 683645
Date 11/06/2017
Public
Document Table of Contents

3.10.3. Defining the Contents of the fpga.bin File

You may arbitrarily define the contents of the fpga.bin file in a Custom Platform because it passes from the Intel® FPGA SDK for OpenCL™ to the Custom Platform as a black box.
Table 9.  Contents of the s5_net fpga.bin File

The contents of the fpga.bin file in the Stratix® V Network Reference Platform are defined as an Executable and Linkable Format (ELF) library that organizes the various fields.

Field Description
.acl.sof The full programming bits for the compiled design.
.acl.core.rbf The CvP programming bits for the compiled design.
.acl.periph.hash The hash of the periph.rbf file that the current compilation generates. This hash is also embedded in the on-chip Hash ROM. The Hash ROM is compared against this hash to determine, ahead of time, whether CvP programming will succeed.
.acl.compile_revision The name of the compiled Intel® Quartus® Prime project revision.
.acl.pcie.dev The device ID of the PCIe® controller. The PCIe device ID is set to match the FPGA part number (for example, D8). This field is compared to the FPGA part number to ensure that the programming files correspond to the device undergoing programming.
.acl.base_revision.rbf The full-FPGA .rbf file of the base revision compilation used to generate the post-fit netlist. This .rbf file must be the power-on image of the FPGA. All other designs can be programmed via CvP on top of this image.
.acl.base_revision.periph.hash The hash of the periph.rbf file of the base revision compilation from which the post-fit netlist is derived. This field is retrieved from the base.aocx file and should match the .acl.periph.hash field for any SDK user compilation.