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2.1. Initializing Your Custom Platform
2.2. Removing Unused Hardware
2.3. Integrating Your Custom Platform with the Intel® FPGA SDK for OpenCL™
2.4. Setting up the Software Development Environment
2.5. Building the Software in Your Custom Platform
2.6. Establishing Host Communication
2.7. Connecting the Memory
2.8. Integrating an OpenCL Kernel
2.9. Programming Your FPGA Quickly Using CvP
2.10. Guaranteeing Timing Closure
2.11. Troubleshooting
3.1. Host-FPGA Communication over PCIe
3.2. DDR3 as Global Memory for OpenCL Applications
3.3. QDRII as Heterogeneous Memory for OpenCL Applications
3.4. Host Connection to OpenCL Kernels
3.5. Implementation of UDP Cores as OpenCL Channels
3.6. FPGA System Design
3.7. Guaranteed Timing Closure
3.8. Addition of Timing Constraints
3.9. Connection to the Intel® FPGA SDK for OpenCL™
3.10. FPGA Programming Flow
3.11. Host-to-Device MMD Software Implementation
3.12. OpenCL Utilities Implementation
3.13. Stratix V Network Reference Platform Implementation Considerations
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3.10.3. Defining the Contents of the fpga.bin File
You may arbitrarily define the contents of the fpga.bin file in a Custom Platform because it passes from the Intel® FPGA SDK for OpenCL™ to the Custom Platform as a black box.
Field | Description |
---|---|
.acl.sof | The full programming bits for the compiled design. |
.acl.core.rbf | The CvP programming bits for the compiled design. |
.acl.periph.hash | The hash of the periph.rbf file that the current compilation generates. This hash is also embedded in the on-chip Hash ROM. The Hash ROM is compared against this hash to determine, ahead of time, whether CvP programming will succeed. |
.acl.compile_revision | The name of the compiled Intel® Quartus® Prime project revision. |
.acl.pcie.dev | The device ID of the PCIe® controller. The PCIe device ID is set to match the FPGA part number (for example, D8). This field is compared to the FPGA part number to ensure that the programming files correspond to the device undergoing programming. |
.acl.base_revision.rbf | The full-FPGA .rbf file of the base revision compilation used to generate the post-fit netlist. This .rbf file must be the power-on image of the FPGA. All other designs can be programmed via CvP on top of this image. |
.acl.base_revision.periph.hash | The hash of the periph.rbf file of the base revision compilation from which the post-fit netlist is derived. This field is retrieved from the base.aocx file and should match the .acl.periph.hash field for any SDK user compilation. |