Intel® FPGA SDK for OpenCL™: Stratix® V Network Reference Platform Porting Guide

ID 683645
Date 11/06/2017
Public
Document Table of Contents

2.11. Troubleshooting

Set Intel® FPGA SDK for OpenCL™ -specific environment variables to help troubleshoot Custom Platform design problems.
Table 2.   Intel® FPGA SDK for OpenCL™ -Specific Environment Variables for Identifying Custom Platform Design Problems
Environment Variable Description
ACL_HAL_DEBUG Set this variable to a value of 1 to 5 to enable increasing debug output from the Hardware Abstraction Layer (HAL), which interfaces directly with the MMD layer.
ACL_PCIE_DEBUG Set this variable to a value of 1 to 10000 to enable increasing debug output from the MMD. This variable setting is useful for confirming that the version ID register was read correctly and the UniPHY IP cores are calibrated.
ACL_PCIE_JTAG_CABLE Set this variable to override the default quartus_pgm argument that specifies the cable number. The default is cable 1. If there are multiple Intel FPGA Download Cable, you can specify a particular one here.
ACL_PCIE_JTAG_DEVICE_INDEX Set this variable to override the default quartus_pgm argument that specifies the FPGA device index. By default, this variable has a value of 1. If the FPGA is not the first device in the JTAG chain, you can customize the value.
CL_CONTEXT_COMPILER_MODE_INTELFPGA Unset this variable or set it to a value of 3. The OpenCL™ host runtime reprograms the FPGA as needed, which it does at least once during initialization. To prevent the host application from programming the FPGA, set this variable to a value of 3.
Important: When setting CL_CONTEXT_COMPILER_MODE_INTELFPGA, only use a value of 3.