Arria® 10 FPGA Development Kit User Guide

Download PDF
ID 683526
Date 5/15/2024
Public
Document Table of Contents
Document Table of Contents x
1. Arria® 10 FPGA Development Kit Overview 2. Getting Started 3. Development Board Setup 4. Board Test System 5. Board Update Portal 6. Board Components A. Additional Information
1. Arria® 10 FPGA Development Kit Overview x
1.1. General Description 1.2. Recommended Operating Conditions 1.3. Handling the Board
2. Getting Started x
2.1. Installing the Subscription Edition Software 2.2. Development Kit Package 2.3. Installing the Intel® FPGA Download Cable Driver
2.1. Installing the Subscription Edition Software x
2.1.1. Activating Your License
3. Development Board Setup x
3.1. Applying Power to the Board 3.2. Default Switch and Jumper Settings 3.3. Default Switch and Resistor Settings 3.4. Factory Reset
4. Board Test System x
4.1. Preparing the Board 4.2. Running the Board Test System 4.3. Version Selector 4.4. Using the Board Test System
4.4. Using the Board Test System x
4.4.1. Using the Configure Menu 4.4.2. The System Info Tab 4.4.3. The GPIO Tab 4.4.4. The Flash Tab 4.4.5. The XCVR Tab 4.4.6. The PCIe® Tab 4.4.7. The FMC A Tab 4.4.8. The FMC B Tab 4.4.9. The DDR3 Tab 4.4.10. The DDR4 Tab 4.4.11. The Power Monitor 4.4.12. The Clock Controller
5. Board Update Portal x
5.1. Connecting to the Board Update Portal Web Page
5.1. Connecting to the Board Update Portal Web Page x
5.1.1. Using the Board Update Portal to Update User Designs
6. Board Components x
6.1. Board Overview 6.2. MAX V CPLD System Controller 6.3. FPGA Configuration 6.4. Status Elements 6.5. User Input/Output 6.6. Clock Circuitry 6.7. Components and Interfaces 6.8. Memory 6.9. Board Power Supply 6.10. Daughtercards
6.3. FPGA Configuration x
6.3.1. Configuring the FPGA Using Programmer
6.5. User Input/Output x
6.5.1. User-Defined Push Buttons 6.5.2. User-Defined DIP Switch 6.5.3. User-Defined LEDs 6.5.4. Character LCD 6.5.5. DisplayPort 6.5.6. SDI Video Input/Output Ports
6.6. Clock Circuitry x
6.6.1. On-Board Oscillators 6.6.2. Off-Board Clock I/O
6.7. Components and Interfaces x
6.7.1. PCI Express 6.7.2. 10/100/1000 Ethernet PHY 6.7.3. HiLo External Memory Interface 6.7.4. FMC 6.7.5. QSFP 6.7.6. SFP+ 6.7.7. I2C
6.8. Memory x
6.8.1. Flash 6.8.2. Programming the Flash Using Quartus® Prime Programmer
6.9. Board Power Supply x
6.9.1. Power Distribution System 6.9.2. Power Measurement
6.10. Daughtercards x
6.10.1. External Memory Interface
6.10.1. External Memory Interface x
6.10.1.1. DDR3L 6.10.1.2. DDR4 6.10.1.3. RLDRAM 3 6.10.1.4. QDR-IV 6.10.1.5. FMC Loopback Card
6.10.1.5. FMC Loopback Card x
6.10.1.5.1. High Pin Count (HBC) 6.10.1.5.2. Low Pin Count (LPC)
A. Additional Information x
A.1. Document Revision History for the Arria® 10 FPGA Development Kit User Guide A.2. Compliance and Conformity Statements
A.2. Compliance and Conformity Statements x
A.2.1. CE EMI Conformity Caution
1. Arria® 10 FPGA Development Kit Overview
2. Getting Started
3. Development Board Setup
4. Board Test System
5. Board Update Portal
6. Board Components
A. Additional Information

4.4.6. The PCIe® Tab

This tab allows you to run a PCIe® loopback test on your board. You can also load the design and use an oscilloscope to measure an eye diagram of the PCIe® transmit signals.
Figure 21. The PCIe® Tab
Control Description
Status Displays the following status information during a loopback test:

PLL lock—Shows the PLL locked or unlocked state.

Pattern sync—Shows the pattern synced or not synced state. The pattern is considered synced when the start of the data sequence is detected.

Details—Shows the PLL lock and pattern sync status:
Port PCIe® x8 Gen3
PMA Setting Allows you to make changes to the PMA parameters that affect the active transceiver interface. The following settings are available for analysis:

Serial Loopback—Routes signals between the transmitter and the receiver.

VOD—Specifies the voltage output differential of the transmitter buffer.

Pre-emphasis tap
  • 1st pre—Specifies the amount of pre-emphasis on the pre-tap of the transmitter buffer.
  • 2nd pre—Specifies the amount of pre-emphasis on the second pre-tap of the transmitter buffer.
  • 1st post—Specifies the amount of pre-emphasis on the first post tap of the transmitter buffer.
  • 2nd post—Specifies the amount of pre-emphasis on the second post tap of the transmitter buffer.

Equalizer—Specifies the AC gain setting for the receiver equalizer in four stage mode.

DC gain—Specifies the DC gain setting for the receiver equalizer in four stage mode.

VGA—Specifies the VGA gain value.

All PMA settings should be changed as in Figure 20.

Data Type Specifies the type of data contained in the transactions. The following data types are available for analysis:
  • PRBS 7—Selects pseudo-random 7-bit sequences.
  • PRBS 15—Selects pseudo-random 15-bit sequences.
  • PRBS 23—Selects pseudo-random 23-bit sequences.
  • PRBS 31—Selects pseudo-random 31-bit sequences.
  • HF—Selects highest frequency divide-by-2 data pattern 10101010.
  • LF—Selects lowest frequency divide by 33 data pattern.
Error Control Displays data errors detected during analysis and allows you to insert errors:
  • Detected errors—Displays the number of data errors detected in the hardware.
  • Inserted errors—Displays the number of errors inserted into the transmit data stream.
  • Insert Error—Inserts a one-word error into the transmit data stream each time you click the button. Insert Error is only enabled during transaction performance analysis.
  • Clear—Resets the Detected errors and Inserted errors counters to zeroes.
Loopback

Start—Initiates the selected ports transaction performance analysis.

Note: Always click Clear before Start.

Stop—Terminates transaction performance analysis.

TX and RX performance bars—Show the percentage of maximum theoretical data rate that the requested transactions are able to achieve.

Level Two Title