Arria® 10 FPGA Development Kit User Guide

ID 683526
Date 5/15/2024
Public
Document Table of Contents

6.6.2. Off-Board Clock I/O

The development board has input and output clocks which can be driven onto the board. The output clocks can be programmed to different levels and I/O standards according to the FPGA device’s specification.

Table 29.  Off-Board Clock Inputs
Source Schematic Signal Name I/O Standard Arria® 10 FPGA Pin Number Description
J6 CLKIN_SMA 2.5 V - SMA clock input
Table 30.  Off-Board Clock Outputs
Source Schematic Signal Name I/O Standard Arria® 10 FPGA Pin Number Description
J7 SMA_CLK_OUT 1.8 V E24 SMA clock output
J16 SMA_TX_P 1.8 V C42 SMA transfer clocks
J15 SMA_TX_N 1.8 V C41