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Ixiasoft
6.6.2. Off-Board Clock I/O
The development board has input and output clocks which can be driven onto the board. The output clocks can be programmed to different levels and I/O standards according to the FPGA device’s specification.
Source | Schematic Signal Name | I/O Standard | Arria® 10 FPGA Pin Number | Description |
---|---|---|---|---|
J6 | CLKIN_SMA | 2.5 V | - | SMA clock input |
Source | Schematic Signal Name | I/O Standard | Arria® 10 FPGA Pin Number | Description |
---|---|---|---|---|
J7 | SMA_CLK_OUT | 1.8 V | E24 | SMA clock output |
J16 | SMA_TX_P | 1.8 V | C42 | SMA transfer clocks |
J15 | SMA_TX_N | 1.8 V | C41 |