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6.9.1. Power Distribution System
The following figure below shows the power distribution system on the A10 FPGA development board. Regulator efficiencies and sharing are reflected in the currents shown, which are at conservative absolute maximum levels.
Figure 35. Power Distribution System Block Diagram (ES Edition)
Figure 36. Power Distribution System Block Diagram (Power Solution 1)
Figure 37. Power Distribution System Block Diagram (Power Solution 2)