Arria® 10 FPGA Development Kit User Guide

ID 683526
Date 5/15/2024
Public
Document Table of Contents

6.10.1.3. RLDRAM 3

The RLDRAM 3 x 36 (reduced latency DRAM) controller is designed for use in applications requiring high memory throughput, high clock rates and full programmability.

Figure 40. RLDRAM 3 Block Diagram