Arria® 10 FPGA Development Kit User Guide

ID 683526
Date 5/15/2024
Public
Document Table of Contents

6.6.1. On-Board Oscillators

Figure 32.  Arria® 10 GX FPGA Kit Board Clock Inputs and Default Frequencies
Table 28.  On-Board Oscillators
Source Schematic Signal Name Frequency I/O Standard Arria® 10 FPGA Pin Number Application
U14 REFCLK_SMA_P 302.083333 MHz 1.8 V LVDS N37 Transceiver reference clocks Bank-1H
REFCLK_SMA_N 1.8 V LVDS N38
REFCLK_FMCB_P 625 MHz 1.8 V LVDS AA8 FMC B reference clocks
REFCLK_FMCB_N 1.8 V LVDS AA7
REFCLK_FMCA_P 625 MHz 1.8 V LVDS AN8 FMC A reference clocks
REFCLK_FMCA_N 1.8 V LVDS AN7
PCIE_OB_REFCLK_P 100 MHz 1.8 V LVDS AN37 PCIE reference clocks
PCIE_OB_REFCLK_N 1.8 V LVDS AN38
U26 CLK_EMI_P 133.33 MHz 1.8 V LVDS F34 EMI reference clocks
CLK_EMI_N 1.8 V LVDS F35
REFCLK_QSFP_P 644.53125 MHz 1.8 V LVDS R37 QSFP reference clocks
REFCLK_QSFP_N 1.8 V LVDS R38
REFCLK_SFP_P 644.53125 MHz 1.8 V LVDS AA37 SFP reference clocks
REFCLK_SFP_N 1.8 V LVDS AA38
REFCLK_DP_P 270 MHz 1.8 V LVDS AC37 Display port (DP) reference clocks
REFCLK_DP_N 1.8 V LVDS AC38
X1 REFCLK_SDI_P 148.35 MHz 1.8 V LVDS L37 SDI reference clocks
REFCLK_SDI_N 1.8 V LVDS L38
X2 CLK_125_P 125 MHz 1.8 V LVDS BD24 125 MHz reference clocks for Arria® 10 FPGA
CLK_125_N 1.8 V LVDS BC24
X3 100M_OSC_P 100 MHz LVDS AR36, F23, AG37, AC8 Programmable Oscillator default 100MHz
100M_OSC_N LVDS AR37, G23, AG38, AC7
U53 MV_CLK_50 50 MHz 1.8 V - MAX V System Controller clock
CLK_50 1.8 V AU33 Arria® 10 FPGA reference clock