Arria® 10 FPGA Development Kit User Guide

Download PDF
ID 683526
Date 5/15/2024
Public
Document Table of Contents
Document Table of Contents x
1. Arria® 10 FPGA Development Kit Overview 2. Getting Started 3. Development Board Setup 4. Board Test System 5. Board Update Portal 6. Board Components A. Additional Information
1. Arria® 10 FPGA Development Kit Overview x
1.1. General Description 1.2. Recommended Operating Conditions 1.3. Handling the Board
2. Getting Started x
2.1. Installing the Subscription Edition Software 2.2. Development Kit Package 2.3. Installing the Intel® FPGA Download Cable Driver
2.1. Installing the Subscription Edition Software x
2.1.1. Activating Your License
3. Development Board Setup x
3.1. Applying Power to the Board 3.2. Default Switch and Jumper Settings 3.3. Default Switch and Resistor Settings 3.4. Factory Reset
4. Board Test System x
4.1. Preparing the Board 4.2. Running the Board Test System 4.3. Version Selector 4.4. Using the Board Test System
4.4. Using the Board Test System x
4.4.1. Using the Configure Menu 4.4.2. The System Info Tab 4.4.3. The GPIO Tab 4.4.4. The Flash Tab 4.4.5. The XCVR Tab 4.4.6. The PCIe® Tab 4.4.7. The FMC A Tab 4.4.8. The FMC B Tab 4.4.9. The DDR3 Tab 4.4.10. The DDR4 Tab 4.4.11. The Power Monitor 4.4.12. The Clock Controller
5. Board Update Portal x
5.1. Connecting to the Board Update Portal Web Page
5.1. Connecting to the Board Update Portal Web Page x
5.1.1. Using the Board Update Portal to Update User Designs
6. Board Components x
6.1. Board Overview 6.2. MAX V CPLD System Controller 6.3. FPGA Configuration 6.4. Status Elements 6.5. User Input/Output 6.6. Clock Circuitry 6.7. Components and Interfaces 6.8. Memory 6.9. Board Power Supply 6.10. Daughtercards
6.3. FPGA Configuration x
6.3.1. Configuring the FPGA Using Programmer
6.5. User Input/Output x
6.5.1. User-Defined Push Buttons 6.5.2. User-Defined DIP Switch 6.5.3. User-Defined LEDs 6.5.4. Character LCD 6.5.5. DisplayPort 6.5.6. SDI Video Input/Output Ports
6.6. Clock Circuitry x
6.6.1. On-Board Oscillators 6.6.2. Off-Board Clock I/O
6.7. Components and Interfaces x
6.7.1. PCI Express 6.7.2. 10/100/1000 Ethernet PHY 6.7.3. HiLo External Memory Interface 6.7.4. FMC 6.7.5. QSFP 6.7.6. SFP+ 6.7.7. I2C
6.8. Memory x
6.8.1. Flash 6.8.2. Programming the Flash Using Quartus® Prime Programmer
6.9. Board Power Supply x
6.9.1. Power Distribution System 6.9.2. Power Measurement
6.10. Daughtercards x
6.10.1. External Memory Interface
6.10.1. External Memory Interface x
6.10.1.1. DDR3L 6.10.1.2. DDR4 6.10.1.3. RLDRAM 3 6.10.1.4. QDR-IV 6.10.1.5. FMC Loopback Card
6.10.1.5. FMC Loopback Card x
6.10.1.5.1. High Pin Count (HBC) 6.10.1.5.2. Low Pin Count (LPC)
A. Additional Information x
A.1. Document Revision History for the Arria® 10 FPGA Development Kit User Guide A.2. Compliance and Conformity Statements
A.2. Compliance and Conformity Statements x
A.2.1. CE EMI Conformity Caution
1. Arria® 10 FPGA Development Kit Overview
2. Getting Started
3. Development Board Setup
4. Board Test System
5. Board Update Portal
6. Board Components
A. Additional Information

6.1. Board Overview

This section provides an annotated board image and the major component descriptions.
Figure 30. Overview of the Development Board Features (ES Edition)
Figure 31. Overview of the Development Board Features
Table 16.   Arria® 10 GX FPGA Development Board Components
Board Reference Type Description
Featured Devices
U28 FPGA Arria® 10 GX FPGA, 10AX115S2F45I1SG:
  • Adaptive logic modules (ALMs): 427,200
  • LEs (K): 1,150
  • Registers: 1,708,800
  • M20K memory blocks: 2,713
  • Transceiver count: 96
  • Package Type: 1932 BGA
U16 CPLD MAX V CPLD, 2210 LEs, 256FBGA 1.8V VCCINT
Board Reference Type Description
Configuration and Setup Elements
J3 On-Board Intel® FPGA Download Cable II Micro-USB 2.0 connector for programming and debugging the FPGA.
SW3 PCI Express* Control DIP switch Enables PCI Express* link widths x1, x4, and x8.
SW4 JTAG Bypass DIP switch Enables and disables devices in the JTAG chain. This switch is located on the back of the board.
SW5 FPP Configuration DIP Switch Sets the Arria® 10 MSEL pins and VID_EN pin.
SW6 Board settings DIP switch Controls the MAX V CPLD System Controller functions such as clock select, clock enable, factory or user design load from flash and FACTORY signal command sent at power up. This switch is located at the bottom of the board.
S4 CPU reset push button The default reset for the FPGA logic.
S5 Image select push button Toggles the configuration LEDs which selects the program image that loads from flash memory to the FPGA.
S6 Program configuration push button Configures the FPGA from flash memory image based on the program LEDs.
S7 MAX V reset push button The default reset for the MAX V CPLD System Controller.
Board Reference Type Description
Status Elements
D22, D23 JTAG LEDs Indicates transmit or receive activity of the JTAG chain. The TX and RX LEDs flicker if the link is in use and active.
D24, D25 System Console LEDs Indicates the transmit or receive activity of the System Console USB interface. The TX and RX LEDs would flicker if the link is in use and active. The LEDs are either off when not in use or on when in use but idle.
D12, D13, D14 Program LEDs Illuminates to show the LED sequence that determines which flash memory image loads to the FPGA when you press the program load push button.
D17 Configuration done LED Illuminates when the FPGA is configured.
D15 Load LED Illuminates during FPGA configuration.
D16 Error LED Illuminates when the FPGA configuration from flash fails.
D19 Power LED Illuminates when the board is powered on.
D32 Temperature LED Illuminates when an over temperature condition occurs for the FPGA device. Ensure that an adequate heatsink/fan is properly installed..
D26, D27, D28, D29, D30 Ethernet LEDs Shows the connection speed as well as transmit or receive activity.
D33 SDI Cable LED Illuminates to show the transmit or receive activity.
D34, D35, D36, D37, D38 PCI Express* link LEDs You can configure these LEDs to display the PCI Express* link width (x1, x4, x8) and data rate.
D3, D4, D5, D6, D7, D8, D9, D10 User defined LEDs Eight bi-color LEDs (green and red) for 16 user LEDs. Illuminates when driven low.
D1, D2, D11 FMCA LEDs Illuminates for RX, TX, PRSNTn activity.
D18, D20, D21 FMCB LEDs Illuminates for RX, TX, PRSNTn activity.
Board Reference Type Description
Clock Circuitry
X1 SDI reference clock SW6.3 DIP switch controlled:

FS=0: 148.35 MHz

FS=1: 148.50 MHz

X3 Programmable oscillator Si570 programmable oscillator by the clock controller GUI. Default is 100 MHz.
X2 125.0 MHz oscillator 125.0 MHz voltage controlled crystal oscillator for the Ethernet interface.
X4 50 MHz oscillator 50.000 MHz crystal oscillator for general purpose logic.
U26 Quad-output oscillator Si5338 programmable oscillator for clock controller GUI. (Defaults CLK[0:3] = 270 MHz, 644.53125 MHz, 644.53125 MHz, 133.33MHz)
U14 Quad-output oscillator Si5338 programmable oscillator for clock controller GUI. (Defaults CLK[0:3] = 100 MHz, 625 MHz, 625 MHz, 302.083333MHz)
J6 Clock input SMA connector Signal: CLKIN_SMA
J7 Clock output SMA connector Signal: SMA_CLK_OUT
J20, J21 SDI (Serial Digital Interface) transceiver connectors Two sub-miniature version B (SMB) connectors. Drives serial data input/output to or from SDI video port.
Board Reference Type Description
Transceiver Interfaces
J15 SMA connector SMA_TX_N from the left transceiver bank - 1H
J16 SMA connector SMA_TX_P from the left transceiver bank - 1H
Board Reference Type Description
General User Input/Output
SW2 FPGA user DIP switch Octal user DIP switches. When the switch is ON, a logic 0 is selected.
S1, S2, S3 General user push buttons Three user push buttons. Driven low when pressed.
D3, D4, D5, D6, D7, D8, D9, D10 User defined LEDs Eight bi-color user LEDs. Illuminates when driven low.
Board Reference Type Description
Memory Devices
J14 HiLo Connector One x72 memory interface supporting DDR3 (x72), DDR4 (x72), QDR4 (x36), and RLDRAM 3 (x36).
This development kit includes three plugin modules (daughtercards) that use the HiLo connector:
  • DDR4 memory (x72) 1200 MHz
  • DDR3 memory (x72) 1066 MHz, Ping Pong PHY.
  • RLDRAM3 memory (x36) 1,200 MHz
U4, U5 Flash memory ICS - 1GBIT STRATA FLASH, 16-BIT DATA, VCC=VCCQ=1.7V-2.0V, 64-BALL EASY BGA (10MM X 8MM)
Board Reference Type Description
Communication Ports
J22 PCI Express* x8 edge connector Made of gold-plated edge fingers for up to ×8 signaling in either Gen1, Gen2, or Gen3 mode.
J1, J2 FMC Port FPGA mezzanine card ports A and B.
J9 Gbps Ethernet RJ-45 connector RJ-45 connector which provides a 10/100/1000 Ethernet connection via a Marvell 88E1111 PHY and the FPGA-based Triple-Speed Ethernet MAC function in SGMII mode.
J18 QSFP interface Provides four transceiver channels for a 40G QSFP module.
J12 SFP+ connector SFP+ XCVR interface.
J3 Micro-USB connector Embedded Intel® FPGA Download Cable II JTAG for programming the FPGA via a USB cable.
Board Reference Type Description
Display Ports
J5 DisplayPort connector Molex 0.50mm pitch DisplayPort male receptacle, right angle, surface mount, 0.76µm gold plating, 20 circuits with cover.
B2 Character LCD Connector which interfaces to the provided 16 character × 2 line LCD module.
J20, J21 SDI video port Two sub-miniature version B (SMB) connectors that provide a full-duplex SDI interface.
Board Reference Type Description
Power Supply
J22 PCI Express* edge connector Interfaces to a PCI Express* root port such as an appropriate PC motherboard.
J13 DC input jack Accepts a 12-V DC power supply. Do not use this input jack while the board is plugged into a PCI Express* slot.
SW1 Power Switch Switch to power on or off the board when power is supplied from the DC input jack.
J4 PCIe® 2x4 ATX power connector 12-V ATX input. This input must be connected when the board is plugged into a PCIe® root port.
Level Two Title