Arria® 10 FPGA Development Kit User Guide

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ID 683526
Date 5/15/2024
Public
Document Table of Contents
Document Table of Contents x
1. Arria® 10 FPGA Development Kit Overview 2. Getting Started 3. Development Board Setup 4. Board Test System 5. Board Update Portal 6. Board Components A. Additional Information
1. Arria® 10 FPGA Development Kit Overview x
1.1. General Description 1.2. Recommended Operating Conditions 1.3. Handling the Board
2. Getting Started x
2.1. Installing the Subscription Edition Software 2.2. Development Kit Package 2.3. Installing the Intel® FPGA Download Cable Driver
2.1. Installing the Subscription Edition Software x
2.1.1. Activating Your License
3. Development Board Setup x
3.1. Applying Power to the Board 3.2. Default Switch and Jumper Settings 3.3. Default Switch and Resistor Settings 3.4. Factory Reset
4. Board Test System x
4.1. Preparing the Board 4.2. Running the Board Test System 4.3. Version Selector 4.4. Using the Board Test System
4.4. Using the Board Test System x
4.4.1. Using the Configure Menu 4.4.2. The System Info Tab 4.4.3. The GPIO Tab 4.4.4. The Flash Tab 4.4.5. The XCVR Tab 4.4.6. The PCIe® Tab 4.4.7. The FMC A Tab 4.4.8. The FMC B Tab 4.4.9. The DDR3 Tab 4.4.10. The DDR4 Tab 4.4.11. The Power Monitor 4.4.12. The Clock Controller
5. Board Update Portal x
5.1. Connecting to the Board Update Portal Web Page
5.1. Connecting to the Board Update Portal Web Page x
5.1.1. Using the Board Update Portal to Update User Designs
6. Board Components x
6.1. Board Overview 6.2. MAX V CPLD System Controller 6.3. FPGA Configuration 6.4. Status Elements 6.5. User Input/Output 6.6. Clock Circuitry 6.7. Components and Interfaces 6.8. Memory 6.9. Board Power Supply 6.10. Daughtercards
6.3. FPGA Configuration x
6.3.1. Configuring the FPGA Using Programmer
6.5. User Input/Output x
6.5.1. User-Defined Push Buttons 6.5.2. User-Defined DIP Switch 6.5.3. User-Defined LEDs 6.5.4. Character LCD 6.5.5. DisplayPort 6.5.6. SDI Video Input/Output Ports
6.6. Clock Circuitry x
6.6.1. On-Board Oscillators 6.6.2. Off-Board Clock I/O
6.7. Components and Interfaces x
6.7.1. PCI Express 6.7.2. 10/100/1000 Ethernet PHY 6.7.3. HiLo External Memory Interface 6.7.4. FMC 6.7.5. QSFP 6.7.6. SFP+ 6.7.7. I2C
6.8. Memory x
6.8.1. Flash 6.8.2. Programming the Flash Using Quartus® Prime Programmer
6.9. Board Power Supply x
6.9.1. Power Distribution System 6.9.2. Power Measurement
6.10. Daughtercards x
6.10.1. External Memory Interface
6.10.1. External Memory Interface x
6.10.1.1. DDR3L 6.10.1.2. DDR4 6.10.1.3. RLDRAM 3 6.10.1.4. QDR-IV 6.10.1.5. FMC Loopback Card
6.10.1.5. FMC Loopback Card x
6.10.1.5.1. High Pin Count (HBC) 6.10.1.5.2. Low Pin Count (LPC)
A. Additional Information x
A.1. Document Revision History for the Arria® 10 FPGA Development Kit User Guide A.2. Compliance and Conformity Statements
A.2. Compliance and Conformity Statements x
A.2.1. CE EMI Conformity Caution
1. Arria® 10 FPGA Development Kit Overview
2. Getting Started
3. Development Board Setup
4. Board Test System
5. Board Update Portal
6. Board Components
A. Additional Information

6.7.2. 10/100/1000 Ethernet PHY

The Arria® 10 GX FPGA development board supports 10/100/1000 base-T Ethernet using an external Marvell 88E1111 PHY and Triple-Speed Ethernet MAC IP function. The PHY-to-MAC interface employs SGMII using the Arria® 10 GX FPGA LVDS pins in Soft-CDR mode at 1.25 Gbps transmit and receive. In 10-Mb or 100-Mb mode, the SGMII interface still runs at 1.25 GHz but the packet data is repeated 10 or 100 times. The MAC function must be provided in the FPGA for typical networking applications.

The Marvell 88E1111 PHY uses 2.5 V and 1.0 V power rails and requires a 25 MHz reference clock driven from a dedicated oscillator. The PHY interfaces to a HALO HFJ11-1G02E model RJ45 with internal magnetics that can be used for driving copper lines with Ethernet traffic.

Figure 33. SGMII Interface between FPGA (MAC) and Marvell 88E1111 PHY
Table 32.  Ethernet PHY Pin Assignments, Signal Names and Functions

Board Reference (U15)

Schematic Signal Name

FPGA Pin Number

I/O Standard Description

23

ENET_2P5V_INTN

AG13

1.8 V

 Management bus interrupt

25

ENET_2P5V_MDC

AF13

1.8 V

Management bus data clock

24

ENET_2P5V_MDIO

AL18

1.8 V

Management bus data

28

ENET_2P5V_RESETN

AW23

1.8 V

Device reset

59

ENET_LED_LINK10

—

2.5 V

10-Mb link LED

76

ENET_LED_LINK10

—

2.5 V

10-Mb link LED

74

ENET_LED_LINK100

—

2.5 V

100-Mb link LED

60

ENET_LED_LINK1000

—

2.5 V

1000-Mb link LED

73

ENET_LED_LINK1000

—

2.5 V

1000-Mb link LED

58

ENET_LED_RX

—

2.5 V

RX data active LED

69

ENET_LED_RX

—

2.5 V

RX data active LED

68

ENET_LED_TX

—

2.5 V

TX data active LED

30

ENET_RSET

AW23

1.8 V

Device reset

75

ENET_RX_N

AW24

LVDS

SGMII receive channel

77

ENET_RX_P

AV24

SGMII receive channel

81

ENET_TX_N

BD23

SGMII transmit channel

82

ENET_TX_P

BC23

SGMII transmit channel

55

ENET_XTAL_25MHZ

—

2.5 V

25-MHz RGMII transmit clock

31

MDI_N0

—

Media dependent interface

34

MDI_N1

—

41

MDI_N2

—

43

MDI_N3

—

29

MDI_P0

—

33

MDI_P1

—

39

MDI_P2

—

42

MDI_P3

—

Level Two Title