Arria® 10 FPGA Development Kit User Guide

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ID 683526
Date 5/15/2024
Public
Document Table of Contents
Document Table of Contents x
1. Arria® 10 FPGA Development Kit Overview 2. Getting Started 3. Development Board Setup 4. Board Test System 5. Board Update Portal 6. Board Components A. Additional Information
1. Arria® 10 FPGA Development Kit Overview x
1.1. General Description 1.2. Recommended Operating Conditions 1.3. Handling the Board
2. Getting Started x
2.1. Installing the Subscription Edition Software 2.2. Development Kit Package 2.3. Installing the Intel® FPGA Download Cable Driver
2.1. Installing the Subscription Edition Software x
2.1.1. Activating Your License
3. Development Board Setup x
3.1. Applying Power to the Board 3.2. Default Switch and Jumper Settings 3.3. Default Switch and Resistor Settings 3.4. Factory Reset
4. Board Test System x
4.1. Preparing the Board 4.2. Running the Board Test System 4.3. Version Selector 4.4. Using the Board Test System
4.4. Using the Board Test System x
4.4.1. Using the Configure Menu 4.4.2. The System Info Tab 4.4.3. The GPIO Tab 4.4.4. The Flash Tab 4.4.5. The XCVR Tab 4.4.6. The PCIe® Tab 4.4.7. The FMC A Tab 4.4.8. The FMC B Tab 4.4.9. The DDR3 Tab 4.4.10. The DDR4 Tab 4.4.11. The Power Monitor 4.4.12. The Clock Controller
5. Board Update Portal x
5.1. Connecting to the Board Update Portal Web Page
5.1. Connecting to the Board Update Portal Web Page x
5.1.1. Using the Board Update Portal to Update User Designs
6. Board Components x
6.1. Board Overview 6.2. MAX V CPLD System Controller 6.3. FPGA Configuration 6.4. Status Elements 6.5. User Input/Output 6.6. Clock Circuitry 6.7. Components and Interfaces 6.8. Memory 6.9. Board Power Supply 6.10. Daughtercards
6.3. FPGA Configuration x
6.3.1. Configuring the FPGA Using Programmer
6.5. User Input/Output x
6.5.1. User-Defined Push Buttons 6.5.2. User-Defined DIP Switch 6.5.3. User-Defined LEDs 6.5.4. Character LCD 6.5.5. DisplayPort 6.5.6. SDI Video Input/Output Ports
6.6. Clock Circuitry x
6.6.1. On-Board Oscillators 6.6.2. Off-Board Clock I/O
6.7. Components and Interfaces x
6.7.1. PCI Express 6.7.2. 10/100/1000 Ethernet PHY 6.7.3. HiLo External Memory Interface 6.7.4. FMC 6.7.5. QSFP 6.7.6. SFP+ 6.7.7. I2C
6.8. Memory x
6.8.1. Flash 6.8.2. Programming the Flash Using Quartus® Prime Programmer
6.9. Board Power Supply x
6.9.1. Power Distribution System 6.9.2. Power Measurement
6.10. Daughtercards x
6.10.1. External Memory Interface
6.10.1. External Memory Interface x
6.10.1.1. DDR3L 6.10.1.2. DDR4 6.10.1.3. RLDRAM 3 6.10.1.4. QDR-IV 6.10.1.5. FMC Loopback Card
6.10.1.5. FMC Loopback Card x
6.10.1.5.1. High Pin Count (HBC) 6.10.1.5.2. Low Pin Count (LPC)
A. Additional Information x
A.1. Document Revision History for the Arria® 10 FPGA Development Kit User Guide A.2. Compliance and Conformity Statements
A.2. Compliance and Conformity Statements x
A.2.1. CE EMI Conformity Caution
1. Arria® 10 FPGA Development Kit Overview
2. Getting Started
3. Development Board Setup
4. Board Test System
5. Board Update Portal
6. Board Components
A. Additional Information

6.7.1. PCI Express

The Arria® 10 GX FPGA development board is designed to fit entirely into a PC motherboard with a ×8 PCI Express* slot that can accommodate a full height long form factor add-in card. This interface uses the Arria® 10 GX FPGA's PCI Express* hard IP block, saving logic resources for the user logic application. The PCI Express* edge connector has a presence detect feature to allow the motherboard to determine if a card is installed.

The PCI Express* interface supports auto-negotiating channel width from ×1 to ×4 to ×8 by using Altera's PCIe® IP. You can also configure this board to a ×1, ×4, or ×8 interface through a DIP switch that connects the PRSNTn pins for each bus width.

The PCI Express* edge connector has a connection speed of 2.5 Gbps/lane for a maximum of 20 Gbps full-duplex (Gen1), 5.0 Gbps/lane for a maximum of 40 Gbps full-duplex (Gen2), or 8.0 Gbps/lane for a maximum of 64 Gbps full-duplex (Gen3).

The power for the board can be sourced entirely from the PC host when installed into a PC motherboard with the PC's 2x4 ATX auxiliary power connected to the 12V ATX input (J4) of the Arria® 10 development board. Although the board can also be powered by a laptop power supply for use on a lab bench, Altera recommends that you do not power up from both supplies at the same time. Ideal diode power sharing devices have been designed into this board to prevent damages or back-current from one supply to the other.

The PCIE_REFCLK_P signal is a 100 MHz differential input that is driven from the PC motherboard on to this board through the edge connector. This signal connects directly to an Arria® 10 GX FPGA REFCLK input pin pair using DC coupling. This clock is terminated on the motherboard and therefore, no on-board termination is required. This clock can have spread-spectrum properties that change its period between 9.847 ps to 10.203 ps. The I/O standard is High-Speed Current Steering Logic (HCSL). The JTAG and SMB are optional signals in the PCI Express* specification. Therefore, the JTAG signal loopback from PCI Express* TDI to PCI Express* TDO and are not used on this board. The SMB signals are wired to the Arria® 10 GX FPGA but are not required for normal operation.

Table 31.   PCI Express* Pin Assignments, Schematic Signal Names, and Functions
Receive bus Receive bus FPGA Pin Number I/O Standard Description

A11

PCIE_EDGE_PERSTN

BC30

1.8 V

Reset

A14

PCIE_EDGE_REFCLK_N

AL38

LVDS

Motherboard reference clock

A13

PCIE_EDGE_REFCLK_P

AL37

LVDS

Motherboard reference clock

B5

PCIE_EDGE_SMBCLK

BD29

1.8 V

SMB clock

B6

PCIE_EDGE_SMBDAT

AU37

1.8 V

SMB data

A1

PCIE_PRSNT1N

—

—

Link with DIP switch

B17

PCIE_PRSNT2N_X1

—

—

Link with DIP switch

B31

PCIE_PRSNT2N_X4

—

—

Link with DIP switch

B48

PCIE_PRSNT2N_X8

—

—

Link with DIP switch

B15

PCIE_RX_N0

AT39

High Speed Differential I/O

Receive bus

B20

PCIE_RX_N1

AP39

High Speed Differential I/O

Receive bus

B24

PCIE_RX_N2

AN41

High Speed Differential I/O

Receive bus

B28

PCIE_RX_N3

AM39

High Speed Differential I/O

Receive bus

B34

PCIE_RX_N4

AL41

High Speed Differential I/O

Receive bus

B38

PCIE_RX_N5

AK39

High Speed Differential I/O

Receive bus

B42

PCIE_RX_N6

AJ41

High Speed Differential I/O

Receive bus

B46

PCIE_RX_N7

AH39

High Speed Differential I/O

Receive bus

B14

PCIE_RX_P0

AT40

High Speed Differential I/O

Receive bus

B19

PCIE_RX_P1

AP40

High Speed Differential I/O

Receive bus

B23

PCIE_RX_P2

AN42

High Speed Differential I/O

Receive bus

B27

PCIE_RX_P3

AM40

High Speed Differential I/O

Receive bus

B33

PCIE_RX_P4

AL42

High Speed Differential I/O

Receive bus

B37

PCIE_RX_P5

AK40

High Speed Differential I/O

Receive bus

B41

PCIE_RX_P6

AJ42

High Speed Differential I/O

Receive bus

B45

PCIE_RX_P7

AH40

High Speed Differential I/O

Receive bus

A17

PCIE_TX_CN0

BB43

High Speed Differential I/O

Transmit bus

A22

PCIE_TX_CN1

BA41

High Speed Differential I/O

Transmit bus

A26

PCIE_TX_CN2

AY43

High Speed Differential I/O

Transmit bus

A30

PCIE_TX_CN3

AW41

High Speed Differential I/O

Transmit bus

A36

PCIE_TX_CN4

AV43

High Speed Differential I/O

Transmit bus

A40

PCIE_TX_CN5

AU41

High Speed Differential I/O

Transmit bus

A44

PCIE_TX_CN6

AT43

High Speed Differential I/O

Transmit bus

A48

PCIE_TX_CN7

AR41

High Speed Differential I/O

Transmit bus

A16

PCIE_TX_CP0

BB44

High Speed Differential I/O

Transmit bus

A21

PCIE_TX_CP1

BA42

High Speed Differential I/O

Transmit bus

A25

PCIE_TX_CP2

AY44

High Speed Differential I/O

Transmit bus

A29

PCIE_TX_CP3

AW42

High Speed Differential I/O

Transmit bus

A35

PCIE_TX_CP4

AV44

High Speed Differential I/O

Transmit bus

A39

PCIE_TX_CP5

AU42

High Speed Differential I/O

Transmit bus

A43

PCIE_TX_CP6

AT44

High Speed Differential I/O

Transmit bus

A47

PCIE_TX_CP7

AR42

High Speed Differential I/O

Transmit bus

B11

PCIE_WAKEN_R

AY29

1.8 V

Wake signal
Level Two Title