F-Tile CPRI PHY Intel® FPGA IP User Guide

ID 683284
Date 3/28/2022
Public

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5.6. TX Interface (8b/10b)

The TX 8b/10b interface is available only if you enable the Enable reconfiguration to 8b/10b datapath parameter or if you select the 8b/10b CPRI line rate. For the CPRI PHY core to power up in the 64b/66b line rate, the IP core asserts these signals when you reconfigure the core at runtime to enter the 8b/10b line rate.

Table 22.  TX 8b/10b Interface
Port Name Width (Bits) Domain Description
i_tx_d[15:0] 16 o_tx_clkout2 Indicates 8b/10b TX data for the corresponding CPRI PHY channel.
i_tx_c[1:0] 2 o_tx_clkout2 Indicates 8b/10b TX control for the corresponding CPRI PHY channel.
When you transmit the data using the TX 8b/10b interface:
  • The frames are 8b/10b encoded. Each byte in i_tx_d has a corresponding bit in i_tx_c that indicates whether the byte is a control byte or a data byte. For example, i_tx_c[1] is the control bit for i_tx_d[15:8].
  • The byte order for the TX interface flows from right to left and the first byte that the core transmits is i_tx_d[7:0].
  • The first bit that the core transmits is i_tx_d[0].