Visible to Intel only — GUID: nle1613682269045
Ixiasoft
5.1. Clock Signals
5.2. Reset Signals
5.3. TX MII Interface (64b/66b)
5.4. RX MII Interface (64b/66b)
5.5. Status Interface for 64b/66b Line Rate
5.6. TX Interface (8b/10b)
5.7. RX Interface (8b/10b)
5.8. Status Interface for 8b/10b Line Rate
5.9. Serial Interface
5.10. CPRI PHY Reconfiguration Interface
5.11. Datapath Avalon Memory-Mapped Interface
5.12. PMA Avalon Memory-Mapped Interface
Visible to Intel only — GUID: nle1613682269045
Ixiasoft
5.2. Reset Signals
Each of the CPRI PHY Channels in the core has its own set of reset signals. The i_reconfig_reset port is shared.
Port Name | Width (Bits) | Domain | Description |
---|---|---|---|
i_tx_rst_n | 1 | Asynchronous | Resets the selected TX datapath. Active low. |
o_tx_rst_ack_n | 1 | Asynchronous | TX datapath reset acknowledgement. Active low. |
o_tx_ready | 1 | Asynchronous | TX datapath is out of reset and ready. |
i_rx_rst_n | 1 | Asynchronous | Resets the selected RX datapath. Active low. |
o_rx_rst_ack_n | 1 | Asynchronous | RX datapath reset acknowledgement. Active low. |
o_rx_ready | 1 | Asynchronous | RX datapath is out of reset and ready. |
i_reconfig_reset | 1 | i_reconfig_clk | Reconfig reset. Resets the Avalon® memory-mapped interface connections to the F-tile and resets Soft CSR. It does not reset F-tile CSRs. Active high. Must be asserted once upon power-up. |