Visible to Intel only — GUID: gvt1613751784402
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5.1. Clock Signals
5.2. Reset Signals
5.3. TX MII Interface (64b/66b)
5.4. RX MII Interface (64b/66b)
5.5. Status Interface for 64b/66b Line Rate
5.6. TX Interface (8b/10b)
5.7. RX Interface (8b/10b)
5.8. Status Interface for 8b/10b Line Rate
5.9. Serial Interface
5.10. CPRI PHY Reconfiguration Interface
5.11. Datapath Avalon Memory-Mapped Interface
5.12. PMA Avalon Memory-Mapped Interface
Visible to Intel only — GUID: gvt1613751784402
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8. Document Revision History for the F-Tile CPRI PHY Intel FPGA IP User Guide
Document Version | Intel® Quartus® Prime Version | IP Version | Changes |
---|---|---|---|
2022.03.28 | 22.1 | 3.2.0 |
|
2021.12.13 | 21.4 | 3.1.0 |
|
2021.10.04 | 21.3 | 3.0.0 |
|
2021.06.21 | 21.2 | 2.0.0 | Initial release. |