F-Tile CPRI PHY Intel® FPGA IP User Guide

ID 683284
Date 3/28/2022
Public

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Document Table of Contents

8. Document Revision History for the F-Tile CPRI PHY Intel FPGA IP User Guide

Document Version Intel® Quartus® Prime Version IP Version Changes
2022.03.28 22.1 3.2.0
  • Removed support for ModelSim* SE simulator.
  • Added a new parameter: Enable CDR Clock Output.
  • Updated the Required Clock Frequencies section.
2021.12.13 21.4 3.1.0
  • Added support for Xcelium* simulator.
  • Updated the Resource Utilization.
  • Added a new parameter: Enable Debug Endpoint for Datapath and PMA Avalon Memory-Mapped Interface.
2021.10.04 21.3 3.0.0
  • Added support for the following line rates:
    • 1.228 Gbps
    • 3.072 Gbps
    • 6.144 Gbps
  • Updated the following sections with new line rate information:
    • Supported Features
    • Resource Utilization
    • IP Parameter Settings
  • Updated the deterministic latency equations in section: Deterministic Latency.
  • Updated the address range for the IP Registers.
  • Added support for the following simulators:
    • Siemens* EDA Questa* simulator
    • Questa*-Intel® FPGA Edition simulator
2021.06.21 21.2 2.0.0 Initial release.