F-Tile CPRI PHY Intel® FPGA IP User Guide

ID 683284
Date 3/28/2022
Public

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5.11. Datapath Avalon Memory-Mapped Interface

Table 27.  Datapath Avalon Memory-Mapped Interface Signals
Port Name Width (Bits) Domain Description
i_reconfig_eth_addr[13:0] 14 i_reconfig_clk Address for the Datapath Avalon Memory-Mapped Interface CSRs in the selected channel. Using word addressing format.
i_reconfig_eth_read 1 i_reconfig_clk Read command for the Datapath Avalon Memory-Mapped Interface CSRs in the selected channel.
i_reconfig_eth_write 1 i_reconfig_clk Write command for the Datapath Avalon Memory-Mapped Interface CSRs in the selected channel.
o_reconfig_eth_readdata[31:0] 32 i_reconfig_clk Read data from reads to the Datapath Avalon Memory-Mapped Interface CSRs in the selected channel.
o_reconfig_eth_readdatavalid 1 i_reconfig_clk Read data from the Datapath Avalon Memory-Mapped Interface CSRs is valid in the selected channel.
i_reconfig_eth_writedata[31:0] 32 i_reconfig_clk Data for writes to the Datapath Avalon Memory-Mapped Interface CSRs in the selected channel.
o_reconfig_eth_waitrequest 1 i_reconfig_clk Avalon® memory-mapped interface stalling signal for operations on the Datapath Avalon Memory-Mapped Interface CSRs in the selected channel.
i_reconfig_eth_byteenable[3:0] 4 i_reconfig_clk Byte-enable for the Datapath Avalon Memory-Mapped Interface CSRs in the selected channel.