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Ixiasoft
5.1. Clock Signals
5.2. Reset Signals
5.3. TX MII Interface (64b/66b)
5.4. RX MII Interface (64b/66b)
5.5. Status Interface for 64b/66b Line Rate
5.6. TX Interface (8b/10b)
5.7. RX Interface (8b/10b)
5.8. Status Interface for 8b/10b Line Rate
5.9. Serial Interface
5.10. CPRI PHY Reconfiguration Interface
5.11. Datapath Avalon Memory-Mapped Interface
5.12. PMA Avalon Memory-Mapped Interface
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Ixiasoft
5.8. Status Interface for 8b/10b Line Rate
This section lists the status ports for the CPRI PHY 8b/10b line rate. Each CPRI PHY channel has its own status port.
Port Name | Width (Bits) | Domain | Description |
---|---|---|---|
o_rx_patterndetect | 1 | o_rx_clkout2 | The IP core asserts this signal to indicate that K28.5 has been detected in the current word boundary of o_rx_d or o_rx_c and the received data from the RX PMA achieved the word alignment. This interface should be observed in conjunction with o_rx_disperr and i_rx_errdetect. |
o_rx_disperr[1:0] | 2 | o_rx_clkout2 | The IP core asserts this signal to indicate that the IP received 10-bit code or data group in the current word boundary of o_rx_d or o_rx_c has a disparity error.
|
o_rx_errdetect[1:0] | 2 | o_rx_clkout2 | The IP core asserts this signal to indicate that it received 10-bit data group in the o_rx_d or o_rx_c has an 8b/10b code violation.
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