F-Tile CPRI PHY Intel® FPGA IP User Guide

ID 683284
Date 3/28/2022
Public

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5.8. Status Interface for 8b/10b Line Rate

This section lists the status ports for the CPRI PHY 8b/10b line rate. Each CPRI PHY channel has its own status port.
Table 24.  CPRI PHY Status Interface Signals for 8b/10b Interface
Port Name Width (Bits) Domain Description
o_rx_patterndetect 1 o_rx_clkout2 The IP core asserts this signal to indicate that K28.5 has been detected in the current word boundary of o_rx_d or o_rx_c and the received data from the RX PMA achieved the word alignment.

This interface should be observed in conjunction with o_rx_disperr and i_rx_errdetect.

o_rx_disperr[1:0] 2 o_rx_clkout2 The IP core asserts this signal to indicate that the IP received 10-bit code or data group in the current word boundary of o_rx_d or o_rx_c has a disparity error.
  • Bit 0: Indicates status for lower data group.
  • Bit 1: Indicates status for higher data group.
o_rx_errdetect[1:0] 2 o_rx_clkout2 The IP core asserts this signal to indicate that it received 10-bit data group in the o_rx_d or o_rx_c has an 8b/10b code violation.
  • Bit 0: Indicates status for lower data group.
  • Bit 1: Indicates status for higher data group.