Visible to Intel only — GUID: ybl1613681193601
Ixiasoft
5.1. Clock Signals
5.2. Reset Signals
5.3. TX MII Interface (64b/66b)
5.4. RX MII Interface (64b/66b)
5.5. Status Interface for 64b/66b Line Rate
5.6. TX Interface (8b/10b)
5.7. RX Interface (8b/10b)
5.8. Status Interface for 8b/10b Line Rate
5.9. Serial Interface
5.10. CPRI PHY Reconfiguration Interface
5.11. Datapath Avalon Memory-Mapped Interface
5.12. PMA Avalon Memory-Mapped Interface
Visible to Intel only — GUID: ybl1613681193601
Ixiasoft
5.4. RX MII Interface (64b/66b)
Port Name | Width (Bits) | Domain | Description |
---|---|---|---|
o_rx_mii_d[63:0] | 64 | o_rx_clkout2 | RX MII data. Data is in MII encoding. o_rx_mii_d[7:0] holds the first byte that the IP core received on the CPRI link. o_rx_mii_d[0] holds the first bit that the IP core received on the CPRI link. |
o_rx_mii_c[7:0] | 8 | o_rx_clkout2 | RX MII control bits. Each bit corresponds to a byte of RX MII data. o_rx_mii_c[0] corresponds to o_rx_mii_d[7:0], o_rx_mii_c[1] corresponds to o_rx_mii_d[15:8], and so on. If the value of a bit is 1, the corresponding data byte is a control byte. If the value of a bit is 0, the corresponding data byte is data. The Start of Packet byte (0xFB) and End of Packet byte (0xFD) are control bytes. |
Figure 9. Receiving Data Using the RX MII InterfaceThis figure shows how to read packets from the RX MII interface.
- The packets are MII encoded. Each byte in o_rx_mii_d has a corresponding bit in o_rx_mii_c that indicates whether the byte is a control byte or a data byte; for example, o_rx_mii_c[2] is the control bit for o_rx_mii_d[23:16].
- The byte order for the RX MII interface flows from right to left. The first byte that the core receives is o_rx_mii_d[7:0].
- The first bit that the IP receives is o_rx_mii_d[0].