Visible to Intel only — GUID: xej1613492621569
Ixiasoft
5.1. Clock Signals
5.2. Reset Signals
5.3. TX MII Interface (64b/66b)
5.4. RX MII Interface (64b/66b)
5.5. Status Interface for 64b/66b Line Rate
5.6. TX Interface (8b/10b)
5.7. RX Interface (8b/10b)
5.8. Status Interface for 8b/10b Line Rate
5.9. Serial Interface
5.10. CPRI PHY Reconfiguration Interface
5.11. Datapath Avalon Memory-Mapped Interface
5.12. PMA Avalon Memory-Mapped Interface
Visible to Intel only — GUID: xej1613492621569
Ixiasoft
1.1. Supported Features
The F-Tile CPRI PHY Intel® FPGA IP core supports the following features:
- Compliant with the CPRI Specification V7.0 (2015-10-09).
- Supports line bit rates of;
- 1.228 Gbps
- 2.4576 Gbps
- 3.072 Gbps
- 4.9152 Gbps
- 6.144 Gbps
- 9.8304 Gbps
- 10.1376 Gbps with and without RS-FEC
- 12.1651 Gbps with and without RS-FEC
- 24.33024 Gbps with and without RS-FEC
- Supports deterministic latency measurement.
- Provides register access interface to external or on-chip processor, using the Intel® Avalon® memory-mapped interconnect specification.
- Supports Physical Medium Attachment (PMA) adaptation.
CPRI Line Bit Rate (Gbps) | RS-FEC Support | Reference Clock (MHz) | Deterministic Latency Support |
---|---|---|---|
1.2288 | No | 153.6 | Yes |
2.4576 | No | 153.6 | Yes |
3.072 | No | 153.6 | Yes |
4.9152 | No | 153.6 | Yes |
6.144 | No | 153.6 | Yes |
9.8304 | No | 153.6 | Yes |
10.1376 | With and Without | 184.32 | Yes |
12.1651 | With and Without | 184.32 | Yes |
24.33024 | With and Without | 184.32 | Yes |