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Ixiasoft
5.1. Clock Signals
5.2. Reset Signals
5.3. TX MII Interface (64b/66b)
5.4. RX MII Interface (64b/66b)
5.5. Status Interface for 64b/66b Line Rate
5.6. TX Interface (8b/10b)
5.7. RX Interface (8b/10b)
5.8. Status Interface for 8b/10b Line Rate
5.9. Serial Interface
5.10. CPRI PHY Reconfiguration Interface
5.11. Datapath Avalon Memory-Mapped Interface
5.12. PMA Avalon Memory-Mapped Interface
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Ixiasoft
4.2.2. Calculation for 64b/66b Datapath
If the 64b/66b datapath RSFEC is enabled, perform the following steps to configure the DL logic in F-tile before the RX latency calculation:
- Ensure the o_rx_blocklock signal is asserted.
- Read the RSFEC code word position value from e25g_stat_s0_rsfec_cw_pos_rx register, num field using the Datapath Avalon memory-mapped interface.
- Program the RSFEC code word position value to FGT ux_q_dl_ctrl_a_l<x> register, cfg_rx_lat_bit_for_async field using the PMA Avalon memory-mapped interface. The ux_q_dl_ctrl_a_l<x> register is based on the placement of the FGT transceiver:
- FGT15, FGT11, FGT7, FGT3: ux_q_dl_ctrl_a_l3
- FGT14, FGT10, FGT6, FGT2: ux_q_dl_ctrl_a_l2
- FGT13, FGT9, FGT5, FGT1: ux_q_dl_ctrl_a_l1
- FGT12, FGT8, FGT4, FGT0: ux_q_dl_ctrl_a_l0
- Reset the deterministic measure logic for RX datapath by asserting the rx_dl_restart bit at register offset 0x8 using the reconfig_cpri interface.
- Release the reset for deterministic measure logic for RX datapath by clearing the rx_dl_restart bit at register offset 0x8 using the reconfig_cpri interface.