Visible to Intel only — GUID: tmg1613681203468
Ixiasoft
5.1. Clock Signals
5.2. Reset Signals
5.3. TX MII Interface (64b/66b)
5.4. RX MII Interface (64b/66b)
5.5. Status Interface for 64b/66b Line Rate
5.6. TX Interface (8b/10b)
5.7. RX Interface (8b/10b)
5.8. Status Interface for 8b/10b Line Rate
5.9. Serial Interface
5.10. CPRI PHY Reconfiguration Interface
5.11. Datapath Avalon Memory-Mapped Interface
5.12. PMA Avalon Memory-Mapped Interface
Visible to Intel only — GUID: tmg1613681203468
Ixiasoft
5.7. RX Interface (8b/10b)
The RX 8b/10b interface is available only if you enable the Enable reconfiguration to 8b/10b datapath parameter or if you select the 8b/10b CPRI line rate. For the CPRI PHY core to power up in the 64b/66b line rate, the IP core asserts these signals when you reconfigure the core at runtime to enter the 8b/10b line rate.
Port Name | Width (Bits) | Domain | Description |
---|---|---|---|
i_rx_d[15:0] | 16 | o_rx_clkout2 | Indicates 8b/10b RX data for the corresponding CPRI PHY channel. |
i_rx_c[1:0] | 2 | o_rx_clkout2 | Indicates 8b/10b RX control for the corresponding CPRI PHY channel. |
When you transmit the data using the RX 8b/10b interface:
- The frames are 8b/10b encoded. Each byte in i_rx_d has a corresponding bit in i_rx_c that indicates whether the byte is a control byte or a data byte. For example, i_rx_c[0] is the control bit for i_rx_d[7:0].
- The byte order for the RX interface flows from right to left and the first byte that the core receives is i_rx_d[7:0].
- The first bit that the core receives is i_rx_d[0].