Visible to Intel only — GUID: mnv1613681181522
Ixiasoft
5.1. Clock Signals
5.2. Reset Signals
5.3. TX MII Interface (64b/66b)
5.4. RX MII Interface (64b/66b)
5.5. Status Interface for 64b/66b Line Rate
5.6. TX Interface (8b/10b)
5.7. RX Interface (8b/10b)
5.8. Status Interface for 8b/10b Line Rate
5.9. Serial Interface
5.10. CPRI PHY Reconfiguration Interface
5.11. Datapath Avalon Memory-Mapped Interface
5.12. PMA Avalon Memory-Mapped Interface
Visible to Intel only — GUID: mnv1613681181522
Ixiasoft
5.1. Clock Signals
Each CPRI PHY channel has its own pair of datapath clocks and each transceiver has its own reference clock. The reconfiguration clock is shared.
Port name | Width (Bits) | Description |
---|---|---|
system_pll_clk_link | 1 | System PLL clock link port. |
tx_pll_refclk_link | 1 | TX PLL reference clock link port. |
rx_cdr_refclk_link | 1 | RX CDR reference clock link port. |
i_reconfig_clk | 1 | Reconfiguration clock. |
i_sampling_clk | 1 | Sampling clock for deterministic latency logic. |
Signal Name | Width (Bits) | I/O Direction | Description |
---|---|---|---|
o_tx_clkout | 1 | Output | System clock divided by 2. |
o_tx_clkout2 | 1 | Output | Parallel TX clock:
Hold circuits using this clock in reset until o_tx_pll_lock is high. |
o_rx_clkout | 1 | Output | System clock divided by 2. |
o_rx_clkout2 | 1 | Output | Parallel RX recovered clock:
Hold circuits using this clock in reset until o_rx_cdr_lock is high. |
Signal Name | Width (Bits) | I/O Direction | Description |
---|---|---|---|
o_tx_pll_lock | 1 | Output | Indicates the TX PLL driving clock signals from the core is locked. Do not use the o_tx_clkout or o_tx_clkout2 clocks until the o_tx_pll_lock clock is high. |
o_rx_cdr_lock | 1 | Output | Indicates that the recovered clocks are locked to data. Do not use the o_rx_clkout or o_rx_clkout2 clocks until the o_rx_cdr_lock clock is high. |