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5.1. Clock Signals
5.2. Reset Signals
5.3. TX MII Interface (64b/66b)
5.4. RX MII Interface (64b/66b)
5.5. Status Interface for 64b/66b Line Rate
5.6. TX Interface (8b/10b)
5.7. RX Interface (8b/10b)
5.8. Status Interface for 8b/10b Line Rate
5.9. Serial Interface
5.10. CPRI PHY Reconfiguration Interface
5.11. Datapath Avalon Memory-Mapped Interface
5.12. PMA Avalon Memory-Mapped Interface
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1.5. Resource Utilization
This section covers the resource utilization for different variations of the F-Tile CPRI PHY Intel® FPGA IP core using the Intel® Quartus® Prime Pro Edition software version 21.4.
CPRI Line Bit Rate (With number of channel1) |
ALMs | ALUTs | Dedicated Logic Registers | Memory 20K |
---|---|---|---|---|
24.33024 Gbps with RS-FEC | 8826 | 13269 | 9885 | 12 |
24 Gbps without RS-FEC | 8866 | 13267 | 9890 | 12 |
12.1651 Gbps with RS-FEC | 8856 | 13267 | 9890 | 12 |
12.1651 Gbps without RS-FEC | 8856 | 13267 | 9890 | 12 |
10.1376 Gbps with RS-FEC | 8856 | 13267 | 9888 | 12 |
10.1376 Gbps without RS-FEC | 8856 | 13267 | 9888 | 12 |
9.8304 Gbps | 9636 | 13873 | 10969 | 12 |
6.144 Gbps | 9667 | 13875 | 10957 | 12 |
4.9152 Gbps | 9664 | 13878 | 10965 | 12 |
3.072 Gbps | 9667 | 13875 | 10952 | 12 |
2.4576 Gbps | 9666 | 13878 | 10949 | 12 |
1.2288 Gbps | 9686 | 13878 | 10940 | 12 |