F-Tile CPRI PHY Intel® FPGA IP User Guide

ID 683284
Date 3/28/2022
Public

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2.4. IP Core Testbenches

Intel provides a testbench and compilation-only design example that you can generate for the F-Tile CPRI PHY Intel® FPGA IP core.

To generate the testbench, in the F-Tile CPRI PHY Intel® FPGA IP parameter editor, you must first set the parameter values for the IP core variation you intend to generate in your end product. If you do not set the parameter values for your DUT to match the parameter values in your end product, the testbench you generate does not exercise the IP core variation you intend.

The testbench demonstrates XGMII data transfer to PHY with internal serial loopback and performs basic latency calculations. It is not intended to be a substitute for a full verification environment.
Note: A compilation-only design example provides reports of timing and resource utilization. It is not a hardware testing design example.