Visible to Intel only — GUID: xcn1613678003467
Ixiasoft
Visible to Intel only — GUID: xcn1613678003467
Ixiasoft
2.4. IP Core Testbenches
Intel provides a testbench and compilation-only design example that you can generate for the F-Tile CPRI PHY Intel® FPGA IP core.
To generate the testbench, in the F-Tile CPRI PHY Intel® FPGA IP parameter editor, you must first set the parameter values for the IP core variation you intend to generate in your end product. If you do not set the parameter values for your DUT to match the parameter values in your end product, the testbench you generate does not exercise the IP core variation you intend.