F-Tile CPRI PHY Intel® FPGA IP User Guide

ID 683284
Date 3/28/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

5.5. Status Interface for 64b/66b Line Rate

This section lists the status ports for the CPRI PHY 64b/66b line rate. Each CPRI PHY channel has its own status port.
Table 21.  Status Interface Signals for 64b/66b Interface
Port Name Width (Bits) Domain Description
o_rx_pcs_ready 1 Asynchronous The IP core asserts this signal to indicate that the corresponding RX datapath is ready to receive data. The signal deasserts when i_rx_rst_n is deasserted.
o_rx_block_lock 1 Asynchronous The IP core asserts this signal to indicate that 66b block alignment has completed for the corresponding CPRI PHY channel.
o_rx_hi_ber 1 Asynchronous The IP core asserts this signal in accordance with IEEE 802.3 to indicate RX PCS is in Hi-Bit Error Rate (BER) state for the corresponding CPRI PHY channel.
o_tx_hip_ready 1 Asynchronous The IP core asserts this signal after i_tx_rst_n is asserted to indicate that the CPRI PHY has completed all internal initialization, is ready to accept reconfiguration transactions and send data.