Visible to Intel only — GUID: pch1613681218832
Ixiasoft
5.1. Clock Signals
5.2. Reset Signals
5.3. TX MII Interface (64b/66b)
5.4. RX MII Interface (64b/66b)
5.5. Status Interface for 64b/66b Line Rate
5.6. TX Interface (8b/10b)
5.7. RX Interface (8b/10b)
5.8. Status Interface for 8b/10b Line Rate
5.9. Serial Interface
5.10. CPRI PHY Reconfiguration Interface
5.11. Datapath Avalon Memory-Mapped Interface
5.12. PMA Avalon Memory-Mapped Interface
Visible to Intel only — GUID: pch1613681218832
Ixiasoft
5.9. Serial Interface
The CPRI PHY IP core always includes the serial ports.
Port Name | Width | Description |
---|---|---|
o_tx_serial | 1 | TX serial data for the corresponding F-tile CPRI PHY channel. |
o_tx_serial_n | 1 | TX serial data (n) for the corresponding F-tile CPRI PHY channel. |
i_rx_serial | 1 | RX serial data for the corresponding F-tile CPRI PHY channel. |
i_rx_serial_n | 1 | RX serial data (n) for the corresponding F-tile CPRI PHY channel. |