AN 766: Intel® Stratix® 10 Devices, High Speed Signal Interface Layout Design Guideline

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ID 683132
Date 3/12/2019
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Document Table of Contents
Document Table of Contents x
Intel® Stratix® 10 Devices, High Speed Signal Interface Layout Design Guideline
Intel® Stratix® 10 Devices, High Speed Signal Interface Layout Design Guideline x
Intel® Stratix® 10 Devices and Transceiver Channels PCB Stackup Selection Guideline Recommendations for High Speed Signal PCB Routing FPGA Fan-out Region Design CFP2/CFP4 Connector Board Layout Design Guideline QSFP+/zSFP/QSFP28 Connector Board Layout Design Guideline SMA 2.4-mm Layout Design Guideline Tyco/Amphenol Interlaken Connector Design Guideline Electrical Specifications Document Revision History for AN 766: Intel® Stratix® 10 Devices, High Speed Signal Interface Layout Design Guideline
FPGA Fan-out Region Design x
Signal Break-out Recommendations FPGA Fan-out Region Routing Recommendations AC Coupling Capacitor Layout and Optimization Guidelines
Signal Break-out Recommendations x
Option 1: Via-In-Pad Topology Option 2: Dog-bone with GND Cutout at BGA Pad Topology Option 3: Micro-via Topology GND Cutout Under BGA Pads in Fan-out Configuration Comparison of Dog-bone with GND Cutout Under the BGA and Via-in-Pad Configurations Trace Shape Routing at the BGA Void Area (Tear Drop Configuration)
FPGA Fan-out Region Routing Recommendations x
Comparison of Conventional and Recommended Break-out Routing Topologies
Comparison of Conventional and Recommended Break-out Routing Topologies x
Conventional Jog-out Routings with Skew-matching Right After Break-out The Impact of Via Height and Via Anti-pad Over Insertion Loss
AC Coupling Capacitor Layout and Optimization Guidelines x
0201 AC Capacitor 0402 AC Capacitor PCB AC Capacitor Placement Layout Recommendation
0201 AC Capacitor x
Sweeping Anti-pad Radius Sweeping Void Width only on the First GND Plane Under the Capacitor
0402 AC Capacitor x
Sweeping Anti-pad Radius Sweeping Void Width Only on the First GND Plane under the Capacitor Adding a Trace Reference to the 0201 AC Capacitor Adding a Trace Reference to the 0402 AC Capacitor
PCB AC Capacitor Placement Layout Recommendation x
What to Avoid for AC Capacitor Configuration
CFP2/CFP4 Connector Board Layout Design Guideline x
CFP2 Host Connector, Module Assembly, and Pinout CFP4 Host Connector, Module Assembly, and Pinout Recommended PCB Design Guideline at the CFP2/CFP4 Connector CFP4 Design Example and Optimization Performance
CFP4 Design Example and Optimization Performance x
CFP4 Connector Layout: Signal Via, Trace Routing Impact, and Optimization Two Different Break-out Routings at the CFP4 Connector Area CFP4 Connector Routing Topologies Design Example Full CFP4 Channel Analysis Design Example (Excluding the Connector) CFP2 Connector Area Layout
QSFP+/zSFP/QSFP28 Connector Board Layout Design Guideline x
QSFP+ Module Assembly and Pinout Recommended PCB Design Guideline for QSFP+/zQSFP/QSFP28 Channels Recommended QSFP+ Signal Routing QSFP28 Example Design and Performance Optimization
SMA 2.4-mm Layout Design Guideline x
SMA 2.4 mm Molex® Connector Assembly PCB Design Guidelines for Channels Using the 2.4 mm Connector 2.4 mm Example Design Performance
PCB Design Guidelines for Channels Using the 2.4 mm Connector x
Recommended PCB layout Design for Version-A SMA 2.4 mm Connector Recommended PCB layout Design for Version-B SMA 2.4 mm Connector Performance Comparison between Option1 and Option2 layout Other 2.4 mm Connectors 2.4 mm Channel Specifications
Tyco/Amphenol Interlaken Connector Design Guideline x
Connector Signal and Pin Assignment
Connector Signal and Pin Assignment x
PCB Design Guidelines for Channels with 25 Gbps + Interlaken Interface Connector Recommendations Interlaken Channel Interface Performance Example
Electrical Specifications x
CEI 28 Very Short Reach (VSR) Specifications for CFP2/CFP4/QSFP+/QSFP28/zQSFP/SMA 2.4 mm Interlaken Interface Specification
Intel® Stratix® 10 Devices, High Speed Signal Interface Layout Design Guideline

Recommendations for High Speed Signal PCB Routing

To achieve better performance for high speed channels, follow these guidelines:

  • TX and RX signal routing must be isolated using separate stripline layers for critical high speed interfaces above 15 Gbps.
  • Intel recommends that the RX signal routing layer be located above the respective TX signal routing layer. This means that the RX routing layer must be separated from TX routing layer. When FPGA's are located on top layer and all high speed vias are back drilled from bottom, Intel recommends RX layers on upper layers and TX layers on those layers below RX layers. The scenario will be opposite if FPGA's are located on bottom layer. In that case, RX layers are recommended on bottom layers and TX layers are recommended on those layers above RX layers.
    • RX signals are always weaker than TX signals. Obtaining shorter transition via length for RX signals reduces mismatching and reflection, and more RX signal power is received at the device.
    • Most of High Speed Interfaces require AC coupling caps on RX signal lanes. Intel recommends RX routing on upper layers close enough to top layer. By this, designer can achieve shorter signal via transition height and eventually reduce reflection on RX path.
    • AC caps can also be mounted on the bottom layer of the PCB. Intel recommends this for signal data rates below 15 Gbps. In this case, you can select the RX signal routing layer as a stripline as close as to bottom layer as possible.
  • Ensure that you have a good contiguous and un-interupted ground reference plane for high speed signal routing.
    • Avoid using the power plane as reference plane for critical high speed signal routing above 15 Gbps.
    • Void regions along, underneath and above the high speed signal routing is prohibited.
    • Always maintain enough space from the edge of the signal trace to the edge of the void region to avoid mismatching due to lack of sufficient reference plane. Spacing should at least be the signal trace width. Intel recommends to have this space be equal or larger than trace width in break-out region.
    • To avoid cross talk between adjacent pairs, make sure to have enough space between pairs routed on the same layer. The rule is to keep at least 3x (the height of signal to reference plane or the width of signal trace, whichever is larger) for the space between adjacent pairs.
  • You must back drill for all high speed signal transition vias.
    • Back drill can be applied from either top or bottom layer, depending on the FPGA and the connectors that have been mounted on top or bottom layers. This emphasizes which part of via as extra stub is needed to be removed.
  • Remove all non-functional via pads for both signal and GND return path vias.
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