AN 766: Intel® Stratix® 10 Devices, High Speed Signal Interface Layout Design Guideline

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ID 683132
Date 3/12/2019
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Document Table of Contents
Document Table of Contents x
Intel® Stratix® 10 Devices, High Speed Signal Interface Layout Design Guideline
Intel® Stratix® 10 Devices, High Speed Signal Interface Layout Design Guideline x
Intel® Stratix® 10 Devices and Transceiver Channels PCB Stackup Selection Guideline Recommendations for High Speed Signal PCB Routing FPGA Fan-out Region Design CFP2/CFP4 Connector Board Layout Design Guideline QSFP+/zSFP/QSFP28 Connector Board Layout Design Guideline SMA 2.4-mm Layout Design Guideline Tyco/Amphenol Interlaken Connector Design Guideline Electrical Specifications Document Revision History for AN 766: Intel® Stratix® 10 Devices, High Speed Signal Interface Layout Design Guideline
FPGA Fan-out Region Design x
Signal Break-out Recommendations FPGA Fan-out Region Routing Recommendations AC Coupling Capacitor Layout and Optimization Guidelines
Signal Break-out Recommendations x
Option 1: Via-In-Pad Topology Option 2: Dog-bone with GND Cutout at BGA Pad Topology Option 3: Micro-via Topology GND Cutout Under BGA Pads in Fan-out Configuration Comparison of Dog-bone with GND Cutout Under the BGA and Via-in-Pad Configurations Trace Shape Routing at the BGA Void Area (Tear Drop Configuration)
FPGA Fan-out Region Routing Recommendations x
Comparison of Conventional and Recommended Break-out Routing Topologies
Comparison of Conventional and Recommended Break-out Routing Topologies x
Conventional Jog-out Routings with Skew-matching Right After Break-out The Impact of Via Height and Via Anti-pad Over Insertion Loss
AC Coupling Capacitor Layout and Optimization Guidelines x
0201 AC Capacitor 0402 AC Capacitor PCB AC Capacitor Placement Layout Recommendation
0201 AC Capacitor x
Sweeping Anti-pad Radius Sweeping Void Width only on the First GND Plane Under the Capacitor
0402 AC Capacitor x
Sweeping Anti-pad Radius Sweeping Void Width Only on the First GND Plane under the Capacitor Adding a Trace Reference to the 0201 AC Capacitor Adding a Trace Reference to the 0402 AC Capacitor
PCB AC Capacitor Placement Layout Recommendation x
What to Avoid for AC Capacitor Configuration
CFP2/CFP4 Connector Board Layout Design Guideline x
CFP2 Host Connector, Module Assembly, and Pinout CFP4 Host Connector, Module Assembly, and Pinout Recommended PCB Design Guideline at the CFP2/CFP4 Connector CFP4 Design Example and Optimization Performance
CFP4 Design Example and Optimization Performance x
CFP4 Connector Layout: Signal Via, Trace Routing Impact, and Optimization Two Different Break-out Routings at the CFP4 Connector Area CFP4 Connector Routing Topologies Design Example Full CFP4 Channel Analysis Design Example (Excluding the Connector) CFP2 Connector Area Layout
QSFP+/zSFP/QSFP28 Connector Board Layout Design Guideline x
QSFP+ Module Assembly and Pinout Recommended PCB Design Guideline for QSFP+/zQSFP/QSFP28 Channels Recommended QSFP+ Signal Routing QSFP28 Example Design and Performance Optimization
SMA 2.4-mm Layout Design Guideline x
SMA 2.4 mm Molex® Connector Assembly PCB Design Guidelines for Channels Using the 2.4 mm Connector 2.4 mm Example Design Performance
PCB Design Guidelines for Channels Using the 2.4 mm Connector x
Recommended PCB layout Design for Version-A SMA 2.4 mm Connector Recommended PCB layout Design for Version-B SMA 2.4 mm Connector Performance Comparison between Option1 and Option2 layout Other 2.4 mm Connectors 2.4 mm Channel Specifications
Tyco/Amphenol Interlaken Connector Design Guideline x
Connector Signal and Pin Assignment
Connector Signal and Pin Assignment x
PCB Design Guidelines for Channels with 25 Gbps + Interlaken Interface Connector Recommendations Interlaken Channel Interface Performance Example
Electrical Specifications x
CEI 28 Very Short Reach (VSR) Specifications for CFP2/CFP4/QSFP+/QSFP28/zQSFP/SMA 2.4 mm Interlaken Interface Specification
Intel® Stratix® 10 Devices, High Speed Signal Interface Layout Design Guideline

Interlaken Channel Interface Performance Example

The channel in this example is designed for the Interlaken interface using a TYCO Interlaken connector. The board layout recommendations provided above are used in this channel design. This example design is implemented on the Intel® Arria® 10 device development kit.

A TX channel has been selected for these 3D HFSS simulations. The TX channel is routed on layer 26 using a back-drill up to layer 27. The total PCB routing is approximately 3.94 inch using stripline routing with rounded corners.

Figure 105. Stackup Layer and Material Data for the Example Interlaken ChannelThese are the specifications for the example channel:
  • 30 layers
  • Copper Foil - HVLP
  • Surface roughness = 2 µm
  • Back-drill
  • Material = Megtron6
  • Total thickness = 153.3 mil
Figure 106. Interlaken TX Channel for Simulation

The following figures show the host PCB TX channel performance from the FPGA BGA/ball to the Interlaken connector signal pads on the top layer.

Figure 107. Differential Insertion Loss on the Host PCB OnlyResults exclude the Interlaken connector.
Figure 108. Differential Return Loss from the Interlaken Connector Pads on the PCBResults exclude the Interlaken connector.

The insertion loss is below the mentioned specifications in Electrical Specifications chapter, which specifies less than 7 dB insertion loss for the host PCB.

Figure 109. Differential Measured TDR Performance for Various TX Interlaken Channels on an Arria 10 device Development KitResults show performance focused only on the PCB trace impedance and connector fan-out areas for various TX channels
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