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Intel® Stratix® 10 Devices and Transceiver Channels
PCB Stackup Selection Guideline
Recommendations for High Speed Signal PCB Routing
FPGA Fan-out Region Design
CFP2/CFP4 Connector Board Layout Design Guideline
QSFP+/zSFP/QSFP28 Connector Board Layout Design Guideline
SMA 2.4-mm Layout Design Guideline
Tyco/Amphenol Interlaken Connector Design Guideline
Electrical Specifications
Document Revision History for AN 766: Intel® Stratix® 10 Devices, High Speed Signal Interface Layout Design Guideline
Option 1: Via-In-Pad Topology
Option 2: Dog-bone with GND Cutout at BGA Pad Topology
Option 3: Micro-via Topology
GND Cutout Under BGA Pads in Fan-out Configuration
Comparison of Dog-bone with GND Cutout Under the BGA and Via-in-Pad Configurations
Trace Shape Routing at the BGA Void Area (Tear Drop Configuration)
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Intel® Stratix® 10 Devices and Transceiver Channels
Intel® Stratix® 10 devices vary by the number of supported transceivers channels. The figure below shows a magnified view of Intel® Stratix® 10 device F2397B package map.
Figure 1. Intel® Stratix® 10 F2397B Device Floor Plan with Magnified Transceiver Pins and an Application Example
The transceivers pins are located on the edge of device. There are four transceiver dies inside the package that can support up to 96 transceiver channels for F2397B package. The total size for F2397B package (U50) is 50 mm by 50 mm. The BGA pitch is 1 mm.
RED pins are RX pairs and Green pins are TX pairs. (TX pairs are located on the edge of device, while RX pairs are located further into the device)