AN 773: Drive-On-Chip Design Example for Intel® MAX® 10 Devices

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ID 683072
Date 7/26/2023
Public
Document Table of Contents
Document Table of Contents x
1. About the Drive-On-Chip Design Example for Intel® MAX® 10 Devices 2. Features of the Drive-on-Chip Design Example for Intel® MAX® 10 Devices 3. Getting Started with the Drive-On-Chip Design Example for Intel® MAX® 10 Devices 4. Rebuilding the Drive-On-Chip Design Example for Intel® MAX® 10 Devices 5. About the Scaling of Feedback Signals 6. Motor Control Software 7. Functional Description of the Drive-on-Chip Design Example 8. Achieving Timing Closure on a Motor Control Design 9. Design Security Recommendations 10. Reference Documents for the Drive-on-Chip Design Example 11. Document Revision History for AN 773: Drive-on-Chip Design Example for Intel® MAX® 10 Devices
3. Getting Started with the Drive-On-Chip Design Example for Intel® MAX® 10 Devices x
3.1. Software Requirements for the Drive-On-Chip Design Example for Intel® MAX® 10 Devices 3.2. Hardware Requirements for the Drive-On-Chip Design Example for Intel® MAX® 10 Devices 3.3. Downloading and Installing the Design 3.4. Setting Up the Motor Control Board with your Development Board for the Drive-On-Chip Design Example for Intel® MAX® 10 Devices 3.5. Importing the Drive-On-Chip Design Example Software Project 3.6. Configuring the FPGA Hardware for the Drive-On-Chip Design Example for Intel® MAX® 10 Devices 3.7. Programming the Nios II Software to the Device for the Drive-On-Chip Design Example for Intel® MAX® 10 Devices 3.8. Applying Power to the Power Board 3.9. Debugging and Monitoring the Drive-On-Chip Design Example with System Console 3.10. System Console GUI Upper Pane for the Drive-On-Chip Design Example 3.11. System Console GUI Lower Pane for the Drive-On-Chip Design Example 3.12. Controlling the DC-DC Converter 3.13. Tuning the PI Controller Gains 3.14. Controlling the Speed and Position Demonstrations 3.15. Monitoring Performance
3.2. Hardware Requirements for the Drive-On-Chip Design Example for Intel® MAX® 10 Devices x
3.2.1. Preparing the Rechargeable Battery
4. Rebuilding the Drive-On-Chip Design Example for Intel® MAX® 10 Devices x
4.1. Changing the Intel® MAX® 10 ADC Thresholds or Conversion Sequence 4.2. Generating the Qsys System 4.3. Compiling the Hardware in the Intel Quartus Prime Software 4.4. Generating and Building the Nios II BSP for the Drive-On-Chip Design Example 4.5. Software Application Configuration Files 4.6. Compiling the Software Application for the Drive-On-Chip Design Example 4.7. Programming the Design into Flash Memory
4.5. Software Application Configuration Files x
4.5.1. Defining a New Motor or Encoder Type
5. About the Scaling of Feedback Signals x
5.1. Signal Sensing in Sigma-Delta and MAX 10 Integrated ADCs 5.2. Signal Scaling in the Software of the Drive-on-Chip Design Example 5.3. Scale Factors for the Drive-on-Chip Design Example in the System Console Toolkit
6. Motor Control Software x
6.1. Viewing Motor Control Software Help Files
7. Functional Description of the Drive-on-Chip Design Example x
7.1. Processor Subsystem 7.2. Six-channel PWM Interface 7.3. DC Link Monitor 7.4. Drive System Monitor 7.5. Quadrature Encoder Interface 7.6. Sigma-Delta ADC Interface for Drive Axes 7.7. Intel® MAX® 10 ADCs 7.8. ADC Threshold Sink 7.9. DC-DC Converter 7.10. Motor Control Modes 7.11. FOC Subsystem 7.12. DEKF Technique 7.13. Signals 7.14. Registers
7.4. Drive System Monitor x
7.4.1. Drive System Monitor States for the Drive-on-Chip Design Example
7.6. Sigma-Delta ADC Interface for Drive Axes x
7.6.1. Offset Adjustment for Sigma-Delta ADC Interface
7.9. DC-DC Converter x
7.9.1. DC-DC Control Simulink Models 7.9.2. Sigma-Delta ADC Interface for DC-DC Converter
7.9.1. DC-DC Control Simulink Models x
7.9.1.1. DC-DC Control Block 7.9.1.2. Generating VHDL for the DSP Builder for Intel FPGAs Models for the DC-DC Converter
7.9.1.1. DC-DC Control Block x
7.9.1.1.1. DC-DC Model and VHDL Entity Signal Names and Data Format
7.11. FOC Subsystem x
7.11.1. DSP Builder for Intel FPGAs Model for the Drive-on-Chip Designs 7.11.2. Avalon Memory-Mapped Interface 7.11.3. About DSP Builder for Intel FPGAs 7.11.4. DSP Builder for Intel FPGAs Folding 7.11.5. DSP Builder for Intel FPGAs Model Resource Usage 7.11.6. DSP Builder for Intel FPGAs Design Guidelines 7.11.7. Generating VHDL for the DSP Builder Models for the Drive-on-Chip Designs
8. Achieving Timing Closure on a Motor Control Design x
8.1. Optimizing Motor Control Designs
1. About the Drive-On-Chip Design Example for Intel® MAX® 10 Devices
2. Features of the Drive-on-Chip Design Example for Intel® MAX® 10 Devices
3. Getting Started with the Drive-On-Chip Design Example for Intel® MAX® 10 Devices
4. Rebuilding the Drive-On-Chip Design Example for Intel® MAX® 10 Devices
5. About the Scaling of Feedback Signals
6. Motor Control Software
7. Functional Description of the Drive-on-Chip Design Example
8. Achieving Timing Closure on a Motor Control Design
9. Design Security Recommendations
10. Reference Documents for the Drive-on-Chip Design Example
11. Document Revision History for AN 773: Drive-on-Chip Design Example for Intel® MAX® 10 Devices

1. About the Drive-On-Chip Design Example for Intel® MAX® 10 Devices

The design demonstrates synchronous control of up to two three-phase permanent magnet synchronous motors (PMSMs) or brushless DC (BLDC) motors. Also the design controls a bidirectional DC-DC converter from the same FPGA. You can adapt the design to other motor types. The development kit can take power from a standard power supply or from a rechargeable battery pack, which shows the bidirectional power flow and battery state-of-charge estimation features.
Figure 1.  Intel® Tandem Motion-Power 48 V Board with Intel® MAX® 10 FPGA Development Kit

Supported FPGA Development Kits

The design supports the Rev C (or later) Intel® MAX® 10 10M50 FPGA Development Kit. You can modify the design to run it on other Intel FPGA development kits that have an HSMC connector.

Supported Motor Control Boards

Table 1.  Supported Motor Control Boards
Board Vendor Website Power Stage Sample Rate (kHz max) Supported Feedback
Tandem Motion-Power 48 V Board Terasic www.terasic.com MOSFET 125 Quadrature encoder, resolver, sensorless, trapezoidal

The design requires you to attach a power board to the FPGA development kit. The power board must, at a minimum, implement the motor drive electronics (e.g., IGBT or MOSFET switches), current and voltage feedback signal conditioning and DC link power bus to provide power to the motor via the inverter. The design requires position feedback for some control algorithms.

AC and Servo Drive Systems

AC and servo drive system designs comprise multiple distinct but interdependent functions to realize requirements to meet the performance and efficiency demands of modern motor control systems. The system's primary function is to efficiently control the torque and speed of the AC motor through appropriate control of power electronics. A typical drive system includes:

  • Flexible pulse-width modulation (PWM) circuitry to switch the power stage transistors appropriately
  • Motor control loops for single- or multiaxis control
  • Industrial networking interfaces
  • Position encoder interfaces
  • Current, voltage, and temperature measurement feedback elements.
  • Monitoring functions, for example, for vibration suppression.

The system requires software running on a processor for high-level system control, coordination, and management.

Intel® MAX® 10 Devices and DSP Builder for Intel FPGAs

Intel® MAX® 10 devices offer high-performance fixed- and floating-point DSP functionality, and Nios II soft processors. Intel® MAX® 10 FPGA devices offer a scalable and flexible platform for integration of single- and multiaxis drives on a single FPGA. The design comprises IP, software libraries, and a hardware platform. The design demonstrates DSP Builder for Intel FPGAs and Qsys for creating the the Avalon® Memory-Mapped interface between IP and the processor. The design includes all software and IP components. You can extend and customize the design to meet your own application needs. The design supports partitioning of algorithms between software running on an integrated processor and IP performing portions of the motor control algorithm in the FPGA, to accelerate performance. For example, depending on the performance requirements of your system or the number of axes you need to support, you may implement the field-oriented control (FOC) loop in hardware designed using DSP Builder for Intel FPGAs, or in software on the Nios II processor. The design allows you to connect to the motor and power stages through on chip or off-chip ADCs, feedback encoder devices and transistor gate drive circuitry. You can connect to higher-level automation controllers by adding off-the-shelf IP, for example for industrial Ethernet or CAN.

DSP Builder for Intel FPGAs provides a MATLAB Simulink* based work flow that allows you to create hardware-optimized fixed-latency implementations of algorithms without requiring HDL or hardware programming skills. The design provides fixed- and floating-point examples of the FOC algorithm. You can use the DSP Builder folding feature to reduce the resource usage of the logic compared to a direct parallel implementation.

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