External Memory Interfaces IP Support Center

Introduction

The External Memory Interface (EMIF) support page will help you find information regarding Agilex™ 7, Stratix® 10, Arria® 10, and Cyclone® 10 FPGAs on how to plan, design, implement, and verify your external memory interfaces. You will also find debug, training, and other resource materials on this page.

This page is set up to walk you through the design process from start to finish.

For support resources regarding other FPGAs, search within the following links: Agilex™ 7 FPGA Interface Protocol Design Journey, Agilex™ 5 FPGA Interface Protocol Design Journey, FPGA Documentation, Training Courses, Videos, Design Examples, and Knowledge Base.

1. Device Selection

How Do I Select a Device?

Two tools are available to help you select an FPGA based on your memory requirements:

How Do I Select an External Memory Intellectual Property (IP)?

To learn about the various memory intellectual property (IP) available, refer to the following online training curriculum:

2. User Guides and Documentation

3. EMIF IP Generation

Where Do I Find Information on the EMIF IP?

For information regarding the External Memory Interface (EMIF) Intellectual Property (IP), refer to the following External Memory Interfaces IP User Guides:

• Please refer to 'User Guides' Section

How Do I Generate the EMIF IP?

For detailed information regarding External Memory Interface (EMIF) Intellectual Property (IP) parameters, refer to the following protocol-specific sections within the following EMIF IP User Guides:

How Do I Perform Functional Simulation?

For detailed information on simulating the External Memory Interface (EMIF) Intellectual Property (IP), refer to the following section within the EMIF IP User Guides:

• Agilex™ 7  F & I Series FPGA EMIF IP – Simulating Memory IP
• Agilex™ 7  M series FPGA EMIF IP – Simulating Memory IP
• Agilex™ 5 FPGA EMIF IP – Simulating Memory IP
• Stratix® 10 simulating Memory IP
• Stratix® 10 MX simulating HBM2 IP
• Arria® 10 simulating Memory IP
• Cyclone® 10 simulating Memory IP

For instructions on how to generate an EMIF simulation design example and how to run simulations using the ModelSim*-Intel FPGA simulation software, refer to the following sections within the EMIF IP Design Example User Guides:

• Agilex™ 7 FPGA - Generating the EMIF Design Example for Simulation
• Agilex™ 5 FPGA - Generating the EMIF Design Example for Simulation
• Stratix® 10 generating the EMIF design example for simulation
• Arria® 10 generating the EMIF design example for simulation
• Cyclone® 10 generating the EMIF design example for simulation

For information on how to verify an EMIF design, refer to the 'Training Courses and Video' section for the 'Verifying Memory Interfaces IP' course.

Where Do I Find Information on FPGA Resource and Pin Placement?

For detailed External Memory Interface (EMIF) pin information, refer to the following protocol-specific sections within the following EMIF Intellectual Property (IP) User Guides:

For simplified I/O placement refer to the Interface Planner for an easy-to-use drag-and-drop tool available in the Quartus® Prime Pro Edition software for Arria® 10 and Stratix® 10 FPGAs. Refer to the following videos for information on how to use the Interface Planner and its benefits:

• Introducing BluePrint Platform Designer for External Memory Interface Designs Part 1 of 2
• Introducing BluePrint Platform Designer for External Memory Interface Designs Part 2 of 2

For more information on Interface Planner for resource location assignments, refer to the following online training curriculum:

Additional Resources

What is Ping Pong PHY?

• Ping Pong PHY allows two memory interfaces to share Address and Command buses. This is supported for DDR3 and DDR4 protocols and for Stratix® V, Arria® 10, and Stratix® 10 FPGAs. Refer to the following video for information on the concept of Ping Pong PHY, its benefits, and an analysis of simulation results:
  • DDR4 Ping Pong PHY video

Where Do I Find Information on PHYLite?

• ThePHYLite IP allows you to build custom memory interface PHY blocks for Arria® 10 and Stratix® 10 FPGAs. For detailed information about the PHYLite IP, refer to the following user guide:
  • PHY Lite for Parallel Interfaces FPGA IP User Guide
• For detailed information on how to properly assign pinouts for PHYLite based on different DQ/DQS group sizes, refer to the following video:
  • PHYLite group pin placement video (Note: The video is also applicable to Stratix® 10 devices.)
• The PHYLite IP supports many different I/O standards and termination values on input and output buffers for Arria® 10 and Stratix® 10 FPGAs. Refer to the following video for information on how to create an On-Chip-Termination (OCT) block and how to associate it with the terminated I/O buffer in the PHYLite IP:
  • How to create the OCT block for calibrated termination IO buffer in altera PHYLIte IP

4. Board Design and Simulation

Where Do I Find Information on Board Layout and Design?

For detailed External Memory Interface (EMIF) board layout and design information, refer to the following protocol-specific sections within the following EMIF Intellectual Property (IP) User Guides:

How Do I Perform Board/Channel Simulation?

For information on measuring write-and-read Intersymbol Interference (ISI) and Crosstalk, arranging Command, Address, Control and Data pins, and I/O bank placement restrictions, refer to the following guidelines:

• Arria® 10 device channel simulation guidelines
• Calculating channel loss from DDRx simulation guidelines (Note: The Arria® 10 channel guidelines is also applicable to Stratix® 10 devices)

How Do I Calculate Board Skew and Channel Loss?

Where Do I Find Information on Timing Closure?

For information regarding External Memory Interface (EMIF) timing closure, refer to the following section within the EMIF Intellectual Property (IP) User Guides:

• Agilex™ 7  F & I Series FPGA EMIF IP Timing Closure
• Agilex™ 7 M Series EMIF IP Timing Closure
• Agilex™ 5 Devices EMIF IP Timing Closure
• Stratix® 10 EMIF IP timing closure
• Arria® 10 EMIF IP timing closure
• Cyclone® 10 EMIF IP timing closure

5. Debug

How Do I Debug My External Memory Interface Design?

For information regarding debugging the external memory interface (EMIF) intellectual property (IP), refer to the following section within the EMIF IP User Guides:

• Agilex™ 7 Devices - EMIF IP Debugging
  
  • Agilex™ 7 Devices - EMIF Self-Debug Guide Tool
• Agilex™ 5 Devices - EMIF IP Debugging
• Stratix® 10 EMIF IP debugging
  • Stratix® 10 - EMIF IP Self-Debug Guide Tool
• Arria® 10 EMIF IP debugging
• Cyclone® 10 EMIF IP debugging

How Do I Use the EMIF Debug Toolkit?

For step-by-step instructions on how to daisy-chain multiple memory interfaces for compatibility with the EMIF Debug Toolkit, refer to the following user guide:

• Debugging Multiple Memory Interfaces guide

The Read/Write 2-D Eye Diagram feature available in the EMIF Debug Toolkit generates read-and-write eye diagrams for each data pin. Refer to the following video for information on important voltage reference parameters during the EMIF IP generation process and how to use the 2-D Eye Diagram feature:

• Arria® 10 External Memory Interface Read and Write 2-D Eye Diagram

The Traffic Generator 2.0 allows you to test and debug your external memory interface through customizable traffic and test patterns. Refer to the following guide and videos for detailed information on how to use the Traffic Generator 2.0 feature:

• Traffic Generator 2.0 guide

The Driver Margining feature allows you to capture read-and-write margining data per pin during user-mode traffic. Refer to the following videos for information on the differences between driver margining and calibration margining, and instructions on how to use the Driver Margining feature:

• Driver margining video (Part 1)
• Driver margining video (Part 2)

Where Can I Find Information Regarding Optimizing Controller Performance?

For information regarding controller performance and efficiency, refer to the following section within the External Memory Interfaces (EMIF) Intellectual Property (IP) User Guides:

• Agilex™ 7 F-Series and I-Series optimizing controller performance
• Agilex™ 5 optimizing controller performance
• Stratix® 10 optimizing controller performance
• Stratix® 10 HBM2 controller performance
• Arria® 10 optimizing controller performance
• Cyclone® 10 optimizing controller performance

How Do I Learn About Known Issues Regarding EMIF?

For information on current and known issues regarding the EMIF IP, refer to the Knowledge Base:

• Knowledge base for Agilex™ devices
• Knowledge base for Stratix® 10 devices
• Knowledge base for Arria® 10 devices
• Knowledge base for Cyclone® 10 devices

6. Training Courses and Quick Videos

Training Courses

Agilex™ 7 Device

• Introduction to Memory Interfaces in Agilex™ 7 FPGAs F- & I-Series
• Integration of Memory Interfaces in Agilex™ 7 FPGAs F- & I-Series
• Verifying Memory Interfaces in Agilex™ 7 FPGAs F- & I-Series
• On-Chip debugging of Memory Interfaces in Agilex™ 7 FPGAs F- & I-Series

Arria® 10 and Stratix® 10 Devices

• Introduction to Memory Interfaces IP in FPGA Devices
• Integrating Memory Interfaces IP in FPGA Devices
• Verifying Memory Interfaces IP in FPGA Devices
• On-Chip Debugging of Memory Interfaces IP in FPGA Devices
• High Bandwidth Memory (HBM2) Interfaces in Stratix® 10 MX devices: implementation

Quick Videos

• DDR4 Ping-Pong Phy (devices supported are Stratix® V, Arria® 10, and Stratix® 10)
  
• Introducing BluePrint platform designer for External Memory Interface Design part 1 of 2
• Introducing BluePrint platform designer for External Memory Interface Design part 2 of 2
• Package deskew in FPGA External Memory Interfaces
• Board Timing for Arria® 10 EMIF IP
• Implementing over constraint in Arria® 10 External Memory Interface
• Automated check of FPGA External Memory Interfaces board layout guidelines
• How to build RLDRAM3 EMIF design for Arria® 10 development kit and test the calibration status using EMIF toolkit
• Arria® 10 External Memory Interface toolkit
• Arria® 10 EMIF example traffic generator
• Using the Soft Nios® Processor to debug Arria® 10 External Memory Interfaces

Additional Documentation

Comprehensive list of FPGA devices and product collections categorized by product lifecycle stages.

• FPGA Device and Product Support Collections

Additional Recommended User Guides

For information regarding the External Memory Interface (EMIF) Intellectual Property (IP), refer to the following EMIF IP User Guides:

• External Memory Interfaces Stratix® 10 IP User Guide
• High Bandwidth Memory (HBM2) Interface FPGA IP User Guide
• Arria® 10 External Memory Interfaces IP user guide
• Cyclone® 10 External Memory Interfaces IP user guide
• PHY Lite for Parallel Interfaces FPGA IP Core user guide

Additional Training Courses for External Memory Interfaces

• FPGA Technical Training Catalog