GPU Metrics Reference

Intel® VTune™ Profiler

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ID 766319

Date 10/31/2024

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GPU Metrics Reference

NOTE:

Families of Intel® X^e graphics products starting with Intel® Arc™ Alchemist (formerly DG2) and newer generations feature GPU architecture terminology that shifts from legacy terms. For more information on the terminology changes and to understand their mapping with legacy content, see GPU Architecture Terminology for Intel® X^e Graphics.

Intel® VTune™ Profiler collects and analyzes the following groups of GPU metrics for Intel® HD Graphics and Intel® Iris® Graphics:

Metric Group	List of Metrics
Metrics that are common to all groups below. These metrics are useful to track EU activity.	Computing Threads Started EU Array Active EU Array Idle EU Array Stalled EU Threads Occupancy GPU Core Frequency
Overview metrics	ALU0 Active ALU0 Instructions ALU1 Active ALU1 Instructions ALU2 Active ALU2 Instructions ALU0 and ALU1 Active ALU0 and ALU2 Active ALU and XMX Utilization GPU L3 Atomics L3 Busy L3 Input Available L3 Miss Ratio L3 Output Ready L3 SQ Full L3 Stalled Memory Read Bandwidth Memory Write Bandwidth Multiple Pipe Utilization Sampler Input Available Sampler Output Ready Thread Dispatcher Active TLB Misses XVE Barrier Stall XVE Control Stall XVE Dist or Acc Stall XVE Instruction Fetch Stall XVE Pipe Stall XVE SBID Stall XVE Send Stall XVE XMX Instructions XVE XMX Pipeline Active The fifth and subsequent generations of the Intel® Core™ processor family code named Broadwell include these metrics: L3 Shader Bandwidth Shared Local Memory Read Bandwidth Shared Local Memory Write Bandwidth
Global Memory Accesses metrics	GPU EU Array Usage GPU Instruction Cache L3 Miss Ratio GPU Load Store Cache L3 Miss Ratio GPU Load Store Cache Miss Ratio GPU LSC Atomics GPU LSC Fences GPU Sampler L3 Miss Ratio GPU SLM Atomics GPU SLM Fences L3 Instruction Cache Bandwidth L3 Load Store Cache Read Bandwidth L3 Load Store Cache Write Bandwidth LSC Input Available LSC Output Ready LSC Partial Writes Render/GPGPU Command Streamer Loaded Shared Local Memory Read Bandwidth Shared Local Memory Write Bandwidth SLM Bank Conflicts The fifth and subsequent generations of the Intel® Core™ processor family include these metrics: EU Threads Occupancy EU Send Pipeline Active L3 Shader Bandwidth The first and subsequent generations of the Intel® Arc™ GPUs (codenamed Alchemist) include these metrics: Host-to-GPU Memory Read Bandwidth Host-to-GPU Memory Write Bandwidth L3 Read Bandwidth L3 Write Bandwidth Stack-to-stack Incoming Bandwidth Stack-to-stack Outgoing Bandwidth System Memory Read Bandwidth System Memory Write Bandwidth
Full Compute group of metrics	This group combines metrics from the Overview and Global Memory Accesses groups. Use this information to explore the reasons why the GPU execution units were waiting using the same data view.
Render Basic (preview) metrics:	Samples Killed in PS, pixels Samples Written Samples Blended PS EU Active % PS EU Stall % VS EU Active VS EU Stall
Compute Extended metrics	XVE Bit Manipulation Instructions XVE FP16\BF16\INT8\INT4\INT2 XMX Instructions XVE INT16\INT32\INT64\FP16\FP32\FP64 Instructions
Media Engine metrics	GPU Media Read Requests GPU Media Write Requests Graphics Security Controller Busy Video Codec Busy Video Codec Read Requests Video Codec Write Requests Video Codec 2 Busy Video Codec 2 Read Requests Video Codec 2 Write Requests Video Enhancement Busy Video Enhancement Read Requests Video Enhancement Write Requests Video Enhancement 2 Busy Video Enhancement 2 Read Requests Video Enhancement 2 Write Requests

NOTE:

To analyze Intel® HD Graphics and Intel® Iris® Graphics hardware events, make sure to set up your system for GPU analysis

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