Agilex™ 5 ES Device Errata and User Guidelines

ID 825514
Date 12/09/2024
Public
Document Table of Contents

2. Intel-Specific Errata for the Agilex™ 5 ES Devices

This section lists the Intel® -specific Agilex™ 5 ES Errata. Each listed erratum has an associated status that identifies any planned fixes.

Table 1.  Device Issues
Issue Affected Devices (OPN) Planned Fix
FPGA
Hard Processor System (HPS)
NAND Controller Slave DMA Interface Mapping Size Limited to 4 KB Page Size Agilex™ 5 ES

(A5ED065BBxxAExxR0)

Agilex™ 5 Production

(A5ED065BBxxAExx)

USB 3.1 AxADDR width is limited to 32-bit Agilex™ 5 ES

(A5ED065BBxxAExxR0)

Agilex™ 5 Production

(A5ED065BBxxAExx)

Observe high traffic latencies when EMACs are running at maximum throughput Agilex™ 5 ES

(A5ED065BBxxAExxR0)

Agilex™ 5 Production

(A5ED065BBxxAExx)

Incorrect SD/eMMC controller preset SRS16.BCSDCLK register value Agilex™ 5 ES

(A5ED065BBxxAExxR0)

Agilex™ 5 Production

(A5ED065BBxxAExx)

ECC Checksum Bytes for NAND Flash Data is Miscalculated Agilex™ 5 ES

(A5ED065BBxxAExxR0)

Agilex™ 5 Production

(A5ED065BBxxAExx)

No direct SDM access to HPS SDRAM Agilex™ 5 ES

(A5ED065BBxxAExxR0)

Agilex™ 5 Production

(A5ED065BBxxAExx)

Missing software control to reset individual CPU cores from another CPU core Agilex™ 5 ES

(A5ED065BBxxAExxR0)

Agilex™ 5 Production

(A5ED065BBxxAExx)

HPS External Oscillator (HPS_OSC_CLK) does not work on HPS_IOA_1 and HPS_IOA_2 Agilex™ 5 ES

(A5ED065BBxxAExxR0)

Agilex™ 5 Production

(A5ED065BBxxAExx)

The On-Chip RAM Error Check and Correction (ECC) error injection will not work when using the Linux EDAC driver Agilex™ 5 ES

(A5ED065BBxxAExxR0)

(A5ED013BBxxAExxR0)

Agilex™ 5 Production

(A5ED065BBxxAExx)

(A5ED013BBxxAExx)

Intermittent missing of CoreSight STM hardware events Agilex™ 5 ES

(A5ED065BBxxAExxR0)

(A5ED013BBxxAExxR0)

Agilex™ 5 Production

(A5ED065BBxxAExx)

(A5ED013BBxxAExx)

HPS EMIF read throughput less than target​ Agilex™ 5 ES

(A5ED065BBxxAExxR0)

(A5ED013BBxxAExxR0)

Agilex™ 5 Production

(A5ED065BBxxAExx)

(A5ED013BBxxAExx)

USB 3.1 Software Loopback test is not working Agilex™ 5 ES

(A5ED065BBxxAExxR0)

(A5ED013BBxxAExxR0)

Agilex™ 5 Production

(A5ED065BBxxAExx)

(A5ED013BBxxAExx)

The USB 3.1 controller has a possible glitch on the clock output during U3 to U0 power state transition Agilex™ 5 ES

(A5ED065BBxxAExxR0)

(A5ED013BBxxAExxR0)

No planned fix
The USB 3.1 controller has a spillover condition during IN transfers for bulk endpoint which causes a DBE issue for the ISOC-IN Endpoint Agilex™ 5 ES

(A5ED065BBxxAExxR0)

(A5ED013BBxxAExxR0)

No planned fix
USB 3.1 Controller Device Drops eSS ISOC Data if the ITP Delta Value is Greater than 63 units Agilex™ 5 ES

(A5ED065BBxxAExxR0)

(A5ED013BBxxAExxR0)

No planned fix
The GIC ecc_derr_intr_n interrupt pin cannot be used Agilex™ 5 ES

(A5ED065BBxxAExxR0)

(A5ED013BBxxAExxR0)

Agilex™ 5 Production

(A5ED065BBxxAExx)

(A5ED013BBxxAExx)

HPS I3C1 does not work in Master Mode Agilex™ 5 ES

(A5ED065BBxxAExxR0)

(A5ED013BBxxAExxR0)

Agilex™ 5 Production

(A5ED065BBxxAExx)

(A5ED013BBxxAExx)

HPS I3C0 and I3C1 SDA/SCL pin does not comply with High-Z bus condition Agilex™ 5 ES

(A5ED065BBxxAExxR0)

(A5ED013BBxxAExxR0)

Agilex™ 5 Production

(A5ED065BBxxAExx)

(A5ED013BBxxAExx)

GIC occasionally fails to capture edge-triggered interrupt request Agilex™ 5 ES

(A5ED065BBxxAExxR0)

(A5ED013BBxxAExxR0)

Agilex™ 5 Production

(A5ED065BBxxAExx)

(A5ED013BBxxAExx)

Indeterministic HPS I/O state before device configuration Agilex™ 5 ES

(A5ED065BBxxAExxR0)

Agilex™ 5 Production

(A5ED065BBxxAExx)

LVDS SERDES
LVDS SERDES Transmitter(TX) and LVDS SERDES Receiver(Rx) is not supporting SERDES factor equal to 8 Agilex™ 5 ES

(A5Ex065BBxxAExxR0)

Agilex™ 5 Production

(A5Ex065BBxxAExx)

External Memory Interface (EMIF)
No LPDDR5 Link ECC Support Agilex™ 5 ES

(A5Ex065BBxxAExxR0)

Agilex™ 5 Production

(A5Ex065BBxxAExx)

No LPDDR5 DBI Support Agilex™ 5 ES

(A5Ex065BBxxAExxR0)

Agilex™ 5 Production

(A5Ex065BBxxAExx)

No DDR4 Read DBI Support Agilex™ 5 ES

(A5Ex065BBxxAExxR0)

Agilex™ 5 Production

(A5Ex065BBxxAExx)

No LPDDR4 DBI Support Agilex™ 5 ES

(A5Ex065BBxxAExxR0)

Agilex™ 5 Production

(A5Ex065BBxxAExx)

Reduced EMIF Maximum Frequency Agilex™ 5 ES

(A5ED065BBxxAExxR0)

Agilex™ 5 Production

(A5ED065BBxxAExx)

No Clamshell support for DDR4 Agilex™ 5 ES

(A5Ex065BBxxAExxR0)

Agilex™ 5 Production

(A5Ex065BBxxAExx)

No Clamshell support for single-rank DDR4 Agilex™ 5 ES

(A5Ex013BBxxAExxR0)

Agilex™ 5 Production

(A5Ex013BBxxAExx)

GTS Transceiver
Issue in pause-based Ethernet MAC flow with certain quanta values Agilex™ 5 ES

(A5Ex065BBxxAExxR0)

Agilex™ 5 Production

(A5Ex065BBxxAExx)

Issue in accessing MAC/PCS STATS register during functional reset Agilex™ 5 ES

(A5Ex065BBxxAExxR0)

Agilex™ 5 Production

(A5Ex065BBxxAExx)

USB Compliance Pattern CP7 or CP8 incorrectly generated Agilex™ 5 ES

(A5ED065BBxxAExxR0)

Agilex™ 5 Production

(A5ED065BBxxAExx)

PCIe Gen4 RX lane margining feature is not supported Agilex™ 5 ES

(A5Ex065BBxxAExxR0)

Agilex™ 5 Production

(A5Ex065BBxxAExx)

Dedicated CDR clock output pin (CDRCLKOUT_GTS) not available in bank 1C and 4B causing migration limitation to smaller device family Agilex™ 5 ES

(A5Ex065BB32AExxR0)

Agilex™ 5 Production

(A5Ex065BB32AExx)

Incorrect TLP length decoding for 4 KB memory read request Agilex™ 5 ES

(A5Ex065BBxxAExxR0)

Agilex™ 5 Production

(A5Ex065BBxxAExx)

USB 3.1 SKP order sets deletion does not work properly for clock PPM differences Agilex™ 5 ES

(A5ED065BBxxAExxR0)

Agilex™ 5 Production

(A5ED065BBxxAExx)

TX user clock output does not work for a certain range of VCO frequencies Agilex™ 5 ES

(A5Ex065BBxxAExxR0)

Agilex™ 5 Production

(A5Ex065BBxxAExx)

PERSTn pin from HVIO banks fails to reset PCIe links Agilex™ 5 ES

(A5Ex065BBxxAExxR0)

(A5Ex013BB23AExxR0)

Agilex™ 5 Production

(A5Ex065BBxxAExx)

(A5Ex013BB23AExx)

Aging issue on unconnected used GTS input reference clock pins Agilex™ 5 ES

(A5Ex065BBxxAExxR0)

Agilex™ 5 Production

(A5Ex065BBxxAExx)

GTS Transceivers do not support direct EXTEST JTAG instruction in boundary scan test Agilex™ 5 ES

(A5Ex065BBxxAExxR0)

Agilex™ 5 Production

(A5Ex065BBxxAExx)

IOPLL in HVIO bank cannot drive the GTS transceiver bank. Agilex™ 5 ES

(A5Ex065BBxxAExxR0)

(A5Ex013BB23AExxR0)

Agilex™ 5 Production

(A5Ex065BBxxAExx)

(A5Ex013BB23AExx)

Does not meet the minimum level of the USB 3.1 LFPS Peak-Peak Differential Output Voltage specification (VTX-DIFF-PP-LFPS) Agilex™ 5 ES

(A5Ex065BBxxAExxR0)

(A5Ex013BB23AExxR0)

Agilex™ 5 Production

(A5Ex065BBxxAExx)

(A5Ex013BB23AExx)

Issue in TX and RX stats counters value after MAC stats reset in GTS Ethernet Intel FPGA Hard IP

A5Ex065BBxxAExxR0

(A5Ex013BBxxAExxR0)

Production Devices

(except)

(A5Ex013xxxxAxxx)

(A5Ex008BxxxAxxx)

Issue in FEC codeword binning counter registers report inaccurate values in GTS Ethernet Intel FPGA Hard IP

(A5Ex065BBxxAExxR0)

(A5Ex013BBxxAExxR0)

(A5Ex008BBxxAExxR0)

(A5ED013BBxxAExxR0)

No planned fix
Intermittent Equalization Timeout or Speed Degrade during Link Disable, Hot Reset, Equalization Redo, and Speed Change

(A5Ex065BBxxAExxR0)

(A5Ex013BBxxAExxR0)

(A5Ex008BBxxAExxR0)

(A5ED013BBxxAExxR0)

No planned fix
MIPI DPHY
Reduced MIPI Maximum Frequency Agilex™ 5 ES

(A5Ex065BBxxAExxR0)

Agilex™ 5 Production

(A5Ex065BBxxAExxR0)

Core and I/O
Voltage Sensor may not meet the Agilex 5 Device Data Sheet Specification Agilex™ 5 ES

(A5Ex065BBxxAExxR0)

Agilex™ 5 Production

(A5Ex065BBxxAExx)

Core fabric local temperature sensor may not meet the Agilex 5 Device Data Sheet Specification Agilex™ 5 ES

(A5Ex065BBxxAExxR0)

Agilex™ 5 Production

(A5Ex065BBxxAExx)

Boundary scan test is not feasible for certain I/O pins Agilex™ 5 ES

(A5ED065BBxxAExxR0)

(A5ED013BBxxAExxR0)

Agilex™ 5 Production

(A5ED065BBxxAExx)

(A5ED013BBxxAExx)

HVIO
Duty cycle distortion clock output path could not be achieved for High-voltage I/O (HVIO) in ES devices Agilex™ 5 ES

(A5Ex065BBxxAExxR0)

Agilex™ 5 Production

(A5Ex065BBxxAExx)

HVIO pin may not meet the Leakage Current Specification in Agilex 5 Device Datasheet Agilex™ 5 ES

(A5Ex065BBxxAExxR0)

(A5Ex013BBxxAExxR0)

Agilex™ 5 Production

(A5Ex065BBxxAExx)

(A5Ex065BBxxAExx)

HVIO pin driving strong random state during pre-configuration stage Agilex™ 5 ES

(A5Ex065BBxxAExxR0)

(A5Ex013BBxxAExxR0)

Agilex™ 5 Production

(A5Ex065BBxxAExx)

(A5Ex013BBxxAExx)

Output Pin Utilization Limit per HVIO Bank Agilex™ 5 ES

(A5Ex065BBxxAExxR0)

(A5Ex013BBxxAExxR0)

Agilex™ 5 Production

(except)

(A5Ex008BM16Axxx)

(A5Ex013BM16Axxx)

(A5Ex028BM16Axxx)

(A5Ex013BBM18Axxx)