Agilex™ 5 ES Device Errata and User Guidelines

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ID 825514
Date 12/09/2024
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Document Table of Contents
Document Table of Contents x
1. About This Document 2. Intel-Specific Errata for the Agilex™ 5 ES Devices 3. Arm Errata 4. Agilex™ 5 ES User Guidelines 5. Document Revision History for the Agilex™ 5 ES Device Errata and User Guidelines
1. About This Document x
1.1. Part Number Decoder
2. Intel-Specific Errata for the Agilex™ 5 ES Devices x
2.1. FPGA 2.2. Hard Processor System (HPS) 2.3. LVDS SERDES 2.4. External Memory Interface (EMIF) 2.5. GTS Transceiver 2.6. MIPI DPHY 2.7. Core and I/O 2.8. HVIO
2.2. Hard Processor System (HPS) x
2.2.1. NAND Controller Slave DMA Interface Mapping Size Limited to 4 KB Page Size 2.2.2. USB 3.1 AxADDR width is limited to 32-bit 2.2.3. Observe high traffic latencies when EMACs are running at maximum throughput 2.2.4. Incorrect SD/eMMC controller preset SRS16.BCSDCLK register value 2.2.5. ECC Checksum Bytes for NAND Flash Data is Miscalculated 2.2.6. No direct SDM access to HPS SDRAM 2.2.7. Missing software control to reset individual CPU cores from another CPU core 2.2.8. HPS External Oscillator (HPS_OSC_CLK) does not work on HPS_IOA_1 and HPS_IOA_2 2.2.9. The On-Chip RAM Error Check and Correction (ECC) error injection will not work when using the Linux EDAC driver 2.2.10. Intermittent missing of CoreSight STM hardware events 2.2.11. USB 3.1 Software Loopback test is not working 2.2.12. The USB 3.1 controller has a possible glitch on the clock output during U3 to U0 power state transition 2.2.13. The USB 3.1 controller has a spillover condition during IN transfers for bulk endpoint which causes a DBE issue for the ISOC-IN Endpoint 2.2.14. USB 3.1 Controller Device Drops eSS ISOC Data if the ITP Delta Value is Greater than 63 units 2.2.15. The GIC ecc_derr_intr_n interrupt pin cannot be used 2.2.16. HPS EMIF read throughput less than target​ 2.2.17. HPS I3C1 does not work in Master Mode 2.2.18. HPS I3C0 and I3C1 SDA/SCL pin does not comply with High-Z bus condition 2.2.19. GIC occasionally fails to capture edge-triggered interrupt request 2.2.20. Indeterministic HPS I/O state before device configuration
2.3. LVDS SERDES x
2.3.1. LVDS SERDES Transmitter(TX) and LVDS SERDES Receiver(Rx) is not supporting SERDES factor equal to 8
2.4. External Memory Interface (EMIF) x
2.4.1. No LPDDR5 Link ECC Support 2.4.2. No LPDDR5 DBI Support 2.4.3. No DDR4 Read DBI Support 2.4.4. No LPDDR4 DBI Support 2.4.5. Reduced EMIF Maximum Frequency 2.4.6. No Clamshell support for DDR4 2.4.7. No Clamshell support for single-rank DDR4
2.5. GTS Transceiver x
2.5.1. Issue in pause-based Ethernet MAC flow with certain quanta values 2.5.2. Issue in accessing MAC/PCS STATS register during functional reset 2.5.3. USB Compliance Pattern CP7 or CP8 incorrectly generated 2.5.4. PCIe Gen4 RX lane margining feature is not supported 2.5.5. Dedicated CDR clock output pin (CDRCLKOUT_GTS) not available in bank 1C and 4B causing migration limitation to smaller device family 2.5.6. Incorrect TLP length decoding for 4 KB memory read request 2.5.7. USB 3.1 SKP order sets deletion does not work properly for clock PPM differences 2.5.8. TX user clock output does not work for a certain range of VCO frequencies 2.5.9. PERSTn pin from HVIO banks fails to reset PCIe links 2.5.10. Aging issue on unconnected used GTS input reference clock pins 2.5.11. GTS Transceivers do not support direct EXTEST JTAG instruction in boundary scan test 2.5.12. IOPLL in HVIO bank cannot drive the GTS transceiver bank. 2.5.13. Does not meet the minimum level of the USB 3.1 LFPS Peak-Peak Differential Output Voltage specification (VTX-DIFF-PP-LFPS) 2.5.14. Issue in TX and RX stats counters value after MAC stats reset in GTS Ethernet Intel® FPGA Hard IP 2.5.15. Issue in FEC codeword binning counter registers report inaccurate values in GTS Ethernet Intel® FPGA Hard IP 2.5.16. Intermittent Equalization Timeout or Speed Degrade during Link Disable, Hot Reset, Equalization Redo, and Speed Change
2.6. MIPI DPHY x
2.6.1. Reduced MIPI Maximum Frequency
2.7. Core and I/O x
2.7.1. Voltage Sensor may not meet the Agilex™ 5 Device Data Sheet Specification 2.7.2. Core fabric local temperature sensor may not meet the Agilex™ 5 Device Data Sheet Specification 2.7.3. Boundary scan test is not feasible for certain I/O pins
2.8. HVIO x
2.8.1. Duty cycle distortion clock output path could not be achieved for High-voltage I/O (HVIO) in ES devices 2.8.2. HVIO pin may not meet the Leakage Current Specification in Agilex 5 Device Datasheet 2.8.3. HVIO pin driving strong random state during pre-configuration stage 2.8.4. Output Pin Utilization Limit per HVIO Bank
3. Arm Errata x
3.1. Arm Cortex-A55 Errata 3.2. Arm Cortex-A76 Errata 3.3. CoreSight Errata 3.4. DSU Errata 3.5. SMMU Errata 3.6. GIC Errata
3.1. Arm Cortex-A55 Errata x
3.1.1. 1024718: Update of DBM or AP bits without break-before-make might result in incorrect 3.1.2. 1530923: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation 3.1.3. 2441007: Completion of affected memory accesses might not be guaranteed by completion of a TLBI 3.1.4. 999993: Multiple concurrent ECC errors might cause silent data corruption 3.1.5. 1030596: Cycle count value in timestamp packet might be incorrect 3.1.6. 1030597: Incorrect ETM timestamp value when timestamp and event generation happen on same cycle 3.1.7. 1131793: Stores might prevent progress of an exclusive loop 3.1.8. 1214720: VFP_SPEC PMU event might count incorrectly 3.1.9. 1401736: Non-cacheable loads of mismatched size might not be single-copy atomic 3.1.10. 2109978: Atomic store instructions might not report an External abort or System Error 3.1.11. 2288055: DTR flags not cleared on external debugger access while leaving Debug state 3.1.12. 2342475: Halting step syndrome might be wrong on stepping a Load-Exclusive instruction 3.1.13. 2364958: Some unallocated debug and trace System registers might be trapped by HCR_EL2.TIDCP
3.2. Arm Cortex-A76 Errata x
3.2.1. 1923202: External debugger access to Debug registers might not work during Warm reset 3.2.2. 1946160: Atomic instructions with acquire semantics might not be ordered with respect to older stores with release semantics 3.2.3. 2356586: Continuous failing STREX because of another PE executing prefetch for store behind consistently mispredicted branch 3.2.4. 2743102: The core might deadlock during powerdown sequence 3.2.5. 1346756: TLBI does not treat upper ASID bits as zero when TCR_EL1.AS is 0 3.2.6. 1880110: Noncompliance with prioritization of Exception Catch debug events 3.2.7. 1899433: PFG duplicate reported faults through a Warm reset 3.2.8. 1913780: Some corrected errors might incorrectly increment ERR0MISC0.CECR or ERR0MISC0.CECO 3.2.9. 1930283: The PE might deadlock if Pseudofault Injection is enabled in Debug State 3.2.10. 2001418: DRPS might not execute correctly in Debug state with SCTLR_ELx.IESB set in the current EL 3.2.11. 2019409: ETM trace information records a branch to the next instruction as an N atom 3.2.12. 2052428: An execution of MSR instruction might not update the destination register correctly when an external debugger initiates an APB write operation to update debug registers 3.2.13. 2110726: External APB write to a register located at offset 0x084 might incorrectly issue a write to External Debug Instruction Transfer Register 3.2.14. 2141647: A64 WFI or A64 WFE executed in Debug state suspends execution indefinitely 3.2.15. 2227007: PMU L1D_CACHE_REFILL_OUTER is inaccurate 3.2.16. 2238117: Reads of DISR_EL1 incorrectly return 0s while in Debug State 3.2.17. 2239143: DRPS instruction is not treated as UNDEFINED at EL0 in Debug state 3.2.18. 2263697: L1 Data poison is not cleared by a store 3.2.19. 2307838: ESR_ELx.ISV can be set incorrectly for an external abort on translation table walk 3.2.20. 2391683: Software-step not done after exit from Debug state with an illegal value in DSPSR 3.2.21. 2816904: PE might fail to detect multiple uncorrectable ECC errors in the L1 data cache tag RAM
3.3. CoreSight Errata x
3.3.1. 1991599: ETF flush may not complete and cause data corruption 3.3.2. 1565895: TPIU generates spurious data when stopped 3.3.3. 1456982: TPIU stops accepting trace when FFCR is written 3.3.4. 1456966: TPIU stops accepting trace when the trigger counter is written
3.4. DSU Errata x
3.4.1. 1162044: Incorrect ordering of data cache maintenance operations 3.4.2. 1741320: Use of FUNC_RET power mode prevents thread wakeup in a multithreaded core 3.4.3. 2123467: No response to Debug APB access during a core reset, in Direct connect configuration 3.4.4. 1580900: Incorrect EDPFR value 3.4.5. 1314123: Incorrect ordering after change in cacheability Description Conditions Impact Workaround Category 3.4.6. 1933378: Interconnect DErr on dirty data not reported in RAS registers
3.5. SMMU Errata x
3.5.1. 2214518: Global entries are not always invalidated as expected 3.5.2. 1365437: ATS requests can return global mappings 3.5.3. 2121468: C_BAD_STREAMID not asserted in certain conditions 3.5.4. 1669310: Low performance for invalidation by IPA 3.5.5. 2675030: Multiple Events reported to Event queue for a single transaction 3.5.6. 2666383: PMU event 0x2 (TLB Miss) triggers incorrectly in TCU
3.6. GIC Errata x
3.6.1. 2384374: Failure to forward highest priority interrupt 3.6.2. 1717652: Wake_request may not be delivered if multiple cores are woken by PPIs at the same time 3.6.3. 1494863: SPI recall failure without subsequent trigger 3.6.4. 2023459: Target range check for MAPC/MOVALL/VMAPP/VMOVP ignores bits[51:48] of RDbase field 3.6.5. 2023457: Affinity3 field corrupted by cross-chip 32-bit writes to upper half of GICD_IROUTERn 3.6.6. 1621321: SPI pipe does not always write back single-bit error corrections - including during scrub 3.6.7. 1451068: DCHIPR reads 0 from chips that are not the default owner
4. Agilex™ 5 ES User Guidelines x
4.1. AXI-Lite CSR Interface may enter deadlock condition when the reserved Configuration Status Register of PCS is accessed 4.2. Intel FPGA Power and Thermal Calculator Software 4.3. Power Estimation Guardband
4.2. Intel FPGA Power and Thermal Calculator Software x
4.2.1. How Do I Enable Agilex™ 5 Series in PTC 4.2.2. Power Estimation for Agilex™ 5
1. About This Document
2. Intel-Specific Errata for the Agilex™ 5 ES Devices
3. Arm Errata
4. Agilex™ 5 ES User Guidelines
5. Document Revision History for the Agilex™ 5 ES Device Errata and User Guidelines

3.4.5. 1314123: Incorrect ordering after change in cacheability

Description

If the memory type of an address region is changed from Cacheable to Non-cacheable, and then back again, and rare microarchitectural conditions occur, then stale data might be observed in a cache.

Conditions

  1. An address region of memory is marked in the translation tables as Write-Back Cacheable memory.
  2. The hardware prefetcher starts a data prefetch to an address within this region. This must generate a StashOnce CHI transaction from the core to the DSU, and in some cases the DSU might pass the StashOnce on to the interconnect if the DSU is configured with a CHI master.
  3. The translation tables are updated to change the memory type to Non-cacheable or Device memory. This would involve a break-before-make sequence.
  4. A sequence of cache clean and invalidate instructions are executed to ensure that any Cacheable data in the memory region does not remain in the caches.
  5. The StashOnce transaction and the clean and invalidate transaction to the same address get reordered within the DSU or externally if the StashOnce was sent to the interconnect. This means that the StashOnce transaction can cause the line to be allocated into the cache after the cache maintenance has completed.
  6. A core or other master in the system writes to the region that is now marked Non-cacheable or Device.
  7. The translation tables are changed a second time, to mark the memory as Write-Back Cacheable again.
  8. A load instruction is executed. The load might observe the stale data that was prefetched into the cache, rather than the Non-cacheable data that was written.

Impact

The above sequence is very specific and would typically take a very long time to execute. It requires that the StashOnce transaction is started before the translation table modification, yet does not complete until after both the translation table modification and the cache maintenance. Additionally, the StashOnce and cache maintenance transactions must be reordered by the DSU or interconnect, and this is an unlikely event, especially if they are not started at a similar time. Therefore the combination of these conditions is going to be extremely rare. Furthermore, the change in memory type implies a change of use of the memory, and many such changes of use will not require preservation of the data between uses.

Workaround

No workaround is necessary.

Category

Category C

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