i_pma_cu_clk

input

1

Reset sequencer control signals

i_src_rs_grant

input

4

o_src_rs_req

Output

4

systempll_clk

input

1

Systempll clk

systempll_lock

input

1

Systempll lock signal

directphy_rx_inst0_auto_rx_serial_data_n

input

3

directphy_rx_inst0_auto_i_rx_cdr_refclk_p

input

1

Transceiver refclock input

directphy_rx_inst0_auto_i_rx_coreclkin

input

3

directphy_rx_inst0_auto_i_rx_reset

input

1

Transceiver reset signal

directphy_rx_inst0_auto_i_rx_serial_data

input

3

Transceiver serial data input

directphy_rx_inst0_auto_i_rx_serial_data_n

input

3

directphy_rx_inst0_auto_o_rx_clkout

output

3

Systempll clock divide by 2

directphy_rx_inst0_auto_o_rx_clkout2

output

3

Transceiver word clock

directphy_rx_inst0_auto_o_rx_is_lockedtodata

output

3

Transceiver lock signal

directphy_rx_inst0_auto_o_rx_is_lockedtoref

output

3

directphy_rx_inst0_auto_o_rx_parallel_data

output

240

Transceiver parallel output data

directphy_rx_inst0_auto_o_rx_ready

output

1

Indicate transceiver is ready

directphy_rx_inst0_auto_o_rx_reset_ack

output

1

Indicate transceiver receive the reset signal

directphy_tx_inst0_auto_i_tx_cadence_fast_clk

input

1

TX Cadence clock and control signals

directphy_tx_inst0_auto_i_tx_cadence_slow_clk

input

1

directphy_tx_inst0_auto_o_tx_cadence

output

1

directphy_tx_inst0_auto_i_tx_coreclkin

input

4

directphy_tx_inst0_auto_i_tx_parallel_data

input

320

Transceiver parallel input data

directphy_tx_inst0_auto_i_tx_pll_refclk_p

input

1

Transceiver refclock input

directphy_tx_inst0_auto_i_tx_reset

input

1

Transceiver reset signal

directphy_tx_inst0_auto_o_tx_clkout

output

4

Systempll clock divide by 2

directphy_tx_inst0_auto_o_tx_clkout2

output

4

Transceiver word clock

directphy_tx_inst0_auto_o_tx_pll_locked

output

4

Indicate transceiver pll is locked

directphy_tx_inst0_auto_o_tx_ready

output

1

Indicate transceiver is ready

directphy_tx_inst0_auto_o_tx_reset_ack

output

1

Indicate transceiver receive the reset signal

directphy_tx_inst0_auto_o_tx_serial_data

output

4

Transceiver serial data output

directphy_tx_inst0_auto_o_tx_serial_data_n

output

4

rx_ready

Input

1

Indicate transceiver is ready

audio_CTS

Output

20

HDMI RX core audio interfaces.

For more information, refer to "Sink Interfaces" in GTS HDMI Intel® FPGA IP User Guide .

audio_N

Output

20

audio_data

Output

256

audio_de

Output

1

audio_format

Output

5

audio_info_ai

Output

48

audio_metadata

Output

165

aux_data

Output

72

HDMI RX core auxiliary interfaces.

For more information, refer to "Sink Interfaces" in GTS HDMI Intel® FPGA IP User Guide .

aux_eop

Output

1

aux_error

Output

1

aux_pkt_addr

Output

7

aux_pkt_data

Output

72

aux_pkt_wr

Output

1

aux_sop

Output

1

aux_valid

Output

1

ctrl

Output

12

HDMI RX core control and status ports.

Note: N = symbols per clock

mode

Output

1

edid_ram_access

input

1

HDMI RX EDID RAM access interface.

Assert edid_ram_access when you want to write or read from the EDID RAM, else this signal should be kept low.

When you assert edid_ram_access, the hotplug signal deasserts to allow write or read to the EDID RAM. When EDID RAM access is completed, you should deassert edid_ram_assess and the hotplug signal asserts. The source reads the new EDID due to the hotplug signal toggling.

edid_ram_address

input

8

edid_ram_read

input

1

edid_ram_readdata

Output

8

edid_ram_waitrequest

Output

1

edid_ram_write

input

1

edid_ram_writedata

input

8

i2c_scl

input

1

HDMI RX DDC and SCDC interface.

i2c_sda

inout

1

tmds_config_trans_det

Output

1

For more information, refer to "Sink Interfaces" in GTS HDMI Intel® FPGA IP User Guide .

i2c_clk

input

1

I2c Clock

rx_hpd_req

Output

1

HDMI RX 5V detect and hotplug detect.

For more information, refer to "Sink Interfaces" in GTS HDMI Intel® FPGA IP User Guide .

in_5v_power

input

1

info_avi

Output

123

HDMI RX core sideband signals.

For more information, refer to "Sink Interfaces" in GTS HDMI Intel® FPGA IP User Guide .

info_vsi

Output

61

gcp

Output

6

reset

input

1

Reset signal

scrambler_enable

Output

1

Indicates if the received data is scrambled; corresponds to the Scrambling_Enable field in the SCDC register 0x20 bit 0.

tmds_bit_clock_ratio

Output

1

vid_clk

input

1

Video Clock

locked

Output

1

HDMI RX core video ports.

Note: N = pixels per clock

For more information, refer to "Sink Interfaces" in GTS HDMI Intel® FPGA IP User Guide .

os

input

1

vid_data

Output

96

vid_de

Output

2

vid_hsync

Output

2

vid_lock

Output

1

vid_valid

Output

1

vid_vsync

Output

2

tx_ready

Output

1

Indicate transceiver is ready

audio_CTS

input

20

For more information, refer to "Source Interfaces" in GTS HDMI Intel® FPGA IP User Guide .

audio_N

input

20

audio_clk

input

1

audio_data

input

256

audio_de

input

1

audio_format

input

5

audio_info_ai

input

49

audio_metadata

input

166

audio_mute

input

1

aux_data

input

72

HDMI TX core auxiliary interfaces.

For more information, refer to "Source Interfaces" in GTS HDMI Intel® FPGA IP User Guide .

aux_eop

input

1

aux_ready

Output

1

aux_sop

input

1

aux_valid

input

1

gcp

input

6

HDMI TX core sideband signals.

For more information, refer to "Source Interfaces" in GTS HDMI Intel® FPGA IP User Guide .

info_avi

input

123

info_vsi

input

62

mode

input

1

HDMI TX core control interfaces.

Note: N = pixels per clock

For more information, refer to "Source Interfaces" in GTS HDMI Intel® FPGA IP User Guide .

ctrl

input

12

i2c_master_address

input

4

TX I2C master Avalon memory-mapped interface to I2C master inside the TX core.

Note: These signals are available only when you turn on the Include I2C parameter.

i2c_master_read

input

1

i2c_master_readdata

Output

32

i2c_master_write

input

1

i2c_master_writedata

input

32

i2c_scl

inout

1

I2c Signals

i2c_sda

inout

1

mgmt_clk

input

1

100mhz clock

os

input

2

Oversample input signal

reset

input

1

Reset signals

scrambler_enable

input

1

Indicates if the data is scrambled.

tmds_bit_clock_ratio

input

1

tx_hpd

input

1

HDMI TX hotplug detect interfaces.

tx_hpd_req

Output

1

vid_clk

input

1

Video Clock

vid_data

input

96

HDMI TX core video ports.

Note: N = pixels per clock

For more information, refer to "Source Interfaces" in GTS HDMI Intel® FPGA IP User Guide .

vid_de

input

2

vid_hsync

input

2

vid_overflow

Output

1

vid_ready

Output

1

vid_valid

input

1

vid_vsync

input

2

reset

Input

1

System reset input.

mgmt_clk

Input

1

System clock input (100 MHz).

pll_pixel_refclk

Input

1

Video Actual Pixel clock.

vid_clk

Input

1

HDMI video clock.

rx_vid_lock

Input

3

Indicates HDMI RX video lock status.

rx_vid_valid

Input

1

HDMI RX video interfaces.

rx_vid_de

Input

N

rx_vid_hsync

Input

N

rx_vid_vsync

Input

N

rx_vid_data

Input

N*48

rx_aux_eop

Input

1

HDMI RX auxiliary interfaces.

rx_aux_sop

Input

1

rx_aux_valid

Input

1

rx_aux_data

Input

72

tx_vid_de

Output

N

HDMI TX video interfaces.

Note: N = pixels per clock.

tx_vid_hsync

Output

N

tx_vid_vsync

Output

N

tx_vid_data

Output

N*48

tx_vid_valid

Output

1

tx_vid_ready

Input

1

tx_aux_eop

Output

1

HDMI TX auxiliary interfaces.

tx_aux_sop

Output

1

tx_aux_valid

Output

1

tx_aux_data

Output

72

tx_aux_ready

Input

1

cpu_clk_in_clk_clk

Input

1

CPU clock.

cpu_rst_in_reset_reset

Input

1

CPU reset.

edid_ram_slave_translator_avalon_anti_slave

_0_address

Output

8

EDID RAM access interfaces.

edid_ram_slave_translator_avalon_anti_slave

_0_write

Output

1

edid_ram_slave_translator_avalon_anti_slave

_0_read

Output

1

edid_ram_slave_translator_avalon_anti_slave

_0_readdata

Input

8

edid_ram_slave_translator_avalon_anti_slave

_0_writedata

Output

8

edid_ram_slave_translator_avalon_anti_slave

_0_waitrequest

Input

1

hdmi_i2c_master_i2c_serial_sda_in

Input

1

I2C Master interfaces from the Nios II processor to the output buffer for DDC and SCDC control.

hdmi_i2c_master_i2c_serial_scl_in

Input

1

hdmi_i2c_master_i2c_serial_sda_oe

Output

1

hdmi_i2c_master_i2c_serial_scl_oe

Output

1

redriver_i2c_master_i2c_serial_sda_in

Input

1

I2C Master interfaces from the Nios II processor to the output buffer for TI redriver setting configuration.

redriver_i2c_master_i2c_serial_scl_in

Input

1

redriver_i2c_master_i2c_serial_sda_oe

Output

1

redriver_i2c_master_i2c_serial_scl_oe

Output

1

pio_in0_external_connection_export

Input

32

Parallel input output interfaces.

Bit 0: Connected to the user_dipsw signal to control EDID passthrough mode

Bit 1: TX HPD request

Bit 2: TX transceiver ready

Bits 3: TX reconfiguration done

Bits 4–7: Reserved

Bits 8–11: RX FRL rate

Bit 12: RX TMDS bit clock ratio

Bits 13–16: RX FRL

locked

Bits 17–20: RX FFE

levels

Bit 21: RX alignment locked

Bit 22: RX video lock

Bit 23: User push button 2 to read SCDC registers from external sink

Bits 24–31: Reserved

pio_out0_external_connection_export

Output

32

Parallel input output interfaces.

Bit 0: TX HPD

acknowledgment

Bit 1: TX initialization is done

Bits 2–7: Reserved

Bits 8–11: TX FRL rate

Bits 12–27: TX FRL link training pattern

Bit 28: TX FRL start

Bits 29–31: Reserved

pio_out1_external_connection_export

Output

32

Parallel input output interfaces.

Bit 0: RX EDID RAM

access

Bit 1: RX FLT ready

Bits 2–7: Reserved

Bits 8–15: RX FRL

source test configuration

Bits 16–31: Reserved