GTS HDMI Intel® FPGA IP Design Example User Guide

Download PDF
ID 823528
Date 3/07/2025
Public
Document Table of Contents
Document Table of Contents x
1. GTS HDMI Intel® FPGA IP Design Example Quick Start Guide for Agilex™ 5 Devices 2. Dual Simplex Mode with the HDMI Simplex IP 3. Design Example Variants 4. Simulation Testbench 5. Document Revision History for the GTS HDMI Intel® FPGA IP Design Example User Guide for Agilex™ 5 Devices
1. GTS HDMI Intel® FPGA IP Design Example Quick Start Guide for Agilex™ 5 Devices x
1.1. Design Description 1.2. Supported HDMI Features 1.3. Software Requirements 1.4. Generating the Design 1.5. Simulating the Design
2. Dual Simplex Mode with the HDMI Simplex IP x
2.1. HDMI RX with Integrated Transceiver 2.2. HDMI TX with Integrated Transceiver 2.3. Requirement for Dual Simplex 2.4. Creating Dual Simplex Groups
2.1. HDMI RX with Integrated Transceiver x
2.1.1. HDMI RX Parameters for Integrated Transceiver Mode
2.2. HDMI TX with Integrated Transceiver x
2.2.1. HDMI TX Parameters for Integrated Transceiver Mode
3. Design Example Variants x
3.1. Agilex™ 5 HDMI RX-TX Retransmit with Integrated Transceiver Design Example Variant 3.2. Agilex™ 5 HDMI RX-TX Retransmit Without Integrated Transceiver Design Example Variant
3.1. Agilex™ 5 HDMI RX-TX Retransmit with Integrated Transceiver Design Example Variant x
3.1.1. HDMI RX-TX Retransmit With Integrated Transceiver Design Parameters 3.1.2. Integrated Transceiver With Dual Simplex Block Diagram 3.1.3. Integrated Transceiver Without Dual Simplex Block Diagram 3.1.4. Agilex™ 5 HDMI RX-TX Retransmit With Integrated Transceiver Design Example Top Level Common Blocks 3.1.5. Agilex™ 5 HDMI RX-TX Retransmit With Integrated Transceiver Design Example Interface Signals
3.2. Agilex™ 5 HDMI RX-TX Retransmit Without Integrated Transceiver Design Example Variant x
3.2.1. HDMI RX-TX Retransmit Without Integrated Transceiver Design Parameters 3.2.2. Non-Integrated Transceiver With Dual Simplex Block Diagram 3.2.3. Non-Integrated Transceiver Without Dual Simplex block diagram 3.2.4. Agilex™ 5 HDMI RX-TX Retransmit Without Integrated Transceiver Design Example Top Level Common Blocks 3.2.5. Agilex™ 5 HDMI RX-TX Retransmit Without Integrated Transceiver Design Example Interface Signals
4. Simulation Testbench x
4.1. Non-Integrated Transceiver Simulation Testbench 4.2. Integrated Transceiver (With Dual Simplex) Simulation Testbench 4.3. Simulation Testbench Parameters 4.4. Simulation Time Benchmark
1. GTS HDMI Intel® FPGA IP Design Example Quick Start Guide for Agilex™ 5 Devices
2. Dual Simplex Mode with the HDMI Simplex IP
3. Design Example Variants
4. Simulation Testbench
5. Document Revision History for the GTS HDMI Intel® FPGA IP Design Example User Guide for Agilex™ 5 Devices

2.4. Creating Dual Simplex Groups

To implement dual simplex mode in Agilex™ 5 devices, you must use the Dual Simplex (DS) Assignment Editor to create a dual simplex group.

To create a dual simplex group, you must first create an independent simplex TX IP and an independent simplex RX IP and subsequently use the Dual Simplex Assignment Editor to fit them into the duplex channel.

To create a dual simplex group:
  1. Use Platform Designer to generate each simplex IP separately so that you have your desired set of simplex IPs.
  2. Group your simplex TX IPs and your simplex RX IPs by sharing the same physical channel.
  3. Provide location of each simplex IP in a dual simplex group relative to the starting channel location in the Dual Simplex Assignment Editor:
    1. Open the Dual Simplex Assignment Editor In Quartus® Prime by selecting Assignments > Dual Simplex (DS) Assignment Editor.
    2. Assign your individual simplex IPs to a dual simplex (DS) group:

      The DS Assignment Editor does a quick legality check (protocol level, attribute level) to see if the simplex IPs assigned to a dual simplex group are compatible. If the simplex IPs are not compatible, you get an error message with information.

    3. When you are done assigning simplex IPs to a dual simplex group, save the assignments:

      When you save the DS group, the QSF assignments are added automatically to the project QSF. For example:


  4. Run the Dual Simplex IP Generation in the IP Generation flow to obtain a new multi-channel dual simplex IP:

  5. Instantiate your dual simplex IP in your design and connect to the rest of your design logic.

For more information about dual simplex in Agilex™ 5 GTS transceivers, refer to the GTS Transceiver Dual Simplex Interfaces User Guide.

Related Information
Level Two Title