GTS HDMI Intel® FPGA IP Design Example User Guide

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ID 823528
Date 3/07/2025
Public
Document Table of Contents
Document Table of Contents x
1. GTS HDMI Intel® FPGA IP Design Example Quick Start Guide for Agilex™ 5 Devices 2. Dual Simplex Mode with the HDMI Simplex IP 3. Design Example Variants 4. Simulation Testbench 5. Document Revision History for the GTS HDMI Intel® FPGA IP Design Example User Guide for Agilex™ 5 Devices
1. GTS HDMI Intel® FPGA IP Design Example Quick Start Guide for Agilex™ 5 Devices x
1.1. Design Description 1.2. Supported HDMI Features 1.3. Software Requirements 1.4. Generating the Design 1.5. Simulating the Design
2. Dual Simplex Mode with the HDMI Simplex IP x
2.1. HDMI RX with Integrated Transceiver 2.2. HDMI TX with Integrated Transceiver 2.3. Requirement for Dual Simplex 2.4. Creating Dual Simplex Groups
2.1. HDMI RX with Integrated Transceiver x
2.1.1. HDMI RX Parameters for Integrated Transceiver Mode
2.2. HDMI TX with Integrated Transceiver x
2.2.1. HDMI TX Parameters for Integrated Transceiver Mode
3. Design Example Variants x
3.1. Agilex™ 5 HDMI RX-TX Retransmit with Integrated Transceiver Design Example Variant 3.2. Agilex™ 5 HDMI RX-TX Retransmit Without Integrated Transceiver Design Example Variant
3.1. Agilex™ 5 HDMI RX-TX Retransmit with Integrated Transceiver Design Example Variant x
3.1.1. HDMI RX-TX Retransmit With Integrated Transceiver Design Parameters 3.1.2. Integrated Transceiver With Dual Simplex Block Diagram 3.1.3. Integrated Transceiver Without Dual Simplex Block Diagram 3.1.4. Agilex™ 5 HDMI RX-TX Retransmit With Integrated Transceiver Design Example Top Level Common Blocks 3.1.5. Agilex™ 5 HDMI RX-TX Retransmit With Integrated Transceiver Design Example Interface Signals
3.2. Agilex™ 5 HDMI RX-TX Retransmit Without Integrated Transceiver Design Example Variant x
3.2.1. HDMI RX-TX Retransmit Without Integrated Transceiver Design Parameters 3.2.2. Non-Integrated Transceiver With Dual Simplex Block Diagram 3.2.3. Non-Integrated Transceiver Without Dual Simplex block diagram 3.2.4. Agilex™ 5 HDMI RX-TX Retransmit Without Integrated Transceiver Design Example Top Level Common Blocks 3.2.5. Agilex™ 5 HDMI RX-TX Retransmit Without Integrated Transceiver Design Example Interface Signals
4. Simulation Testbench x
4.1. Non-Integrated Transceiver Simulation Testbench 4.2. Integrated Transceiver (With Dual Simplex) Simulation Testbench 4.3. Simulation Testbench Parameters 4.4. Simulation Time Benchmark
1. GTS HDMI Intel® FPGA IP Design Example Quick Start Guide for Agilex™ 5 Devices
2. Dual Simplex Mode with the HDMI Simplex IP
3. Design Example Variants
4. Simulation Testbench
5. Document Revision History for the GTS HDMI Intel® FPGA IP Design Example User Guide for Agilex™ 5 Devices

1.4. Generating the Design

Use the HDMI Intel® FPGA IP parameter editor in the Quartus® Prime software to generate the design examples.
Estimated Generation Time
Design Generation time (minutes)
Simulation example (simulation) 3
Hardware design example (synthesis) 9
Simulation and hardware design example (simulation + synthesis) 12
Figure 2. Generating the Design Flow
  1. Start Quartus® Prime software from a Nios® V Command Shell as follows:by running the following command:
    1. Start a Nios® V Command Shell session with the following command: 
      <Quartus installation folder>/niosv/bin/niosv-shell
    2. In the Nios® V Command Shell session, start the Quartus® Prime software with the following command: 
      <Quartus installation folder>/quartus

    Starting the Quartus® Prime software from a Nios® V Command Shell ensures that the GTS HDMI Intel® FPGA IP has access to the required Nios® V tools.

  2. Create a project targeting the Agilex™ 5 device family and select the desired device.
  3. In the IP Catalog, locate and double-click GTS HDMI Intel® FPGA IP . The New IP Variant or New IP Variation window appears.
  4. Specify a top-level name for your custom IP variation. The parameter editor saves the IP variation settings in a file named <your_ip>.ip.
  5. Click OK. The parameter editor appears.
  6. On the IP tab, configure the desired parameters for both TX and RX. Common parameters are applied to both TX and RX.
  7. On the Design Example tab, select Agilex™ 5 HDMI RX-TX Retransmit.
  8. Select Simulation to generate the testbench, and select Synthesis to generate the hardware design example.

    You must select at least one of these options to generate the design example files. If you select both, the generation time is longer.

  9. For Generate File Format, select Verilog or VHDL.
  10. For Select Board, select the relevant development kit. You can change the target device using Change Target Device parameter if your board revision does not match the grade of the default targeted device. For Agilex™ 5 devices, the target device is set to A5ED065BB32AE6SR0.
  11. Click Generate Example Design.
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