GTS HDMI Intel® FPGA IP User Guide

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ID 823533
Date 11/25/2024
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Document Table of Contents
Document Table of Contents x
1. GTS HDMI Intel® FPGA IP Quick Reference 2. HDMI Overview 3. Release Information 4. GTS HDMI Intel® FPGA IP Getting Started 5. GTS HDMI Intel® FPGA IP Hardware Design Examples 6. HDMI Source 7. HDMI Sink 8. Transceiver Handling (HDMI Wrapper = HDMI and Transceiver) 9. HDMI Parameters 10. HDMI Simulation Example 11. GTS HDMI Intel® FPGA IP User Guide Archives 12. Document Revision History for the GTS HDMI Intel® FPGA IP User Guide
1. GTS HDMI Intel® FPGA IP Quick Reference x
1.1. Terms and Acronyms
3. Release Information x
3.1. Device Family Support 3.2. Feature Support 3.3. Resource Utilization
4. GTS HDMI Intel® FPGA IP Getting Started x
4.1. Installing and Licensing Intel® FPGA IP Cores 4.2. Specifying IP Parameters and Options
4.1. Installing and Licensing Intel® FPGA IP Cores x
4.1.1. Intel® FPGA IP Evaluation Mode
6. HDMI Source x
6.1. Source Functional Description 6.2. Source Interfaces 6.3. Source Clock Tree 6.4. Valid Video Data 6.5. Source Deep Color Implementation
6.1. Source Functional Description x
6.1.1. Source Scrambler, TMDS/TERC4 Encoder 6.1.2. Source Video Resampler 6.1.3. Source Window of Opportunity Generator 6.1.4. Source Auxiliary Packet Encoder 6.1.5. Source Auxiliary Packet Generators 6.1.6. Source Auxiliary Data Path Multiplexers 6.1.7. Source Auxiliary Control Port 6.1.8. Source Audio Encoder 6.1.9. TX Core-PHY Interface 6.1.10. I2C Controller
6.1.7. Source Auxiliary Control Port x
6.1.7.1. Source General Control Packet (GCP) 6.1.7.2. Source Auxiliary Video Information (AVI) InfoFrame Bit-Fields 6.1.7.3. Source HDMI Vendor Specific InfoFrame (VSI)
6.1.8. Source Audio Encoder x
6.1.8.1. Audio InfoFrame (AI) Bundle Bit-Fields 6.1.8.2. Audio Metadata Bundle Bit-Fields
6.1.9. TX Core-PHY Interface x
6.1.9.1. TX Oversampler 6.1.9.2. Clock Enable Generator
7. HDMI Sink x
7.1. Sink Functional Description 7.2. Sink Interfaces 7.3. Sink Clock Tree 7.4. Sink Deep Color Implementation
7.1. Sink Functional Description x
7.1.1. Sink Word Alignment and Channel Deskew 7.1.2. Sink Descrambler, TMDS/TERC4 Decoder 7.1.3. Sink Auxiliary Decoder 7.1.4. Sink Auxiliary Packet Capture 7.1.5. Sink Video Resampler 7.1.6. Sink Auxiliary Data Port 7.1.7. Sink Audio Decoder 7.1.8. Status and Control Data Channel (SCDC) Interface 7.1.9. RX Core-PHY Interface 7.1.10. I2C Target 7.1.11. I2C and EDID RAM Blocks
7.1.6. Sink Auxiliary Data Port x
7.1.6.1. Sink General Control Packet (GCP) 7.1.6.2. Sink Auxiliary Video Information (AVI) InfoFrame Bit-Fields 7.1.6.3. Sink HDMI Vendor Specific InfoFrame (VSI)
7.1.7. Sink Audio Decoder x
7.1.7.1. Audio InfoFrame (AI) Bundle Bit-Fields 7.1.7.2. Audio Metadata Bundle Bit-Fields
7.1.9. RX Core-PHY Interface x
7.1.9.1. RX Oversampler
8. Transceiver Handling (HDMI Wrapper = HDMI and Transceiver) x
8.1. HDMI RX with Integrated Transceiver 8.2. HDMI TX with Integrated Transceiver 8.3. Creating Dual Simplex Groups
9. HDMI Parameters x
9.1. HDMI Source Parameters 9.2. HDMI Sink Parameters
1. GTS HDMI Intel® FPGA IP Quick Reference
2. HDMI Overview
3. Release Information
4. GTS HDMI Intel® FPGA IP Getting Started
5. GTS HDMI Intel® FPGA IP Hardware Design Examples
6. HDMI Source
7. HDMI Sink
8. Transceiver Handling (HDMI Wrapper = HDMI and Transceiver)
9. HDMI Parameters
10. HDMI Simulation Example
11. GTS HDMI Intel® FPGA IP User Guide Archives
12. Document Revision History for the GTS HDMI Intel® FPGA IP User Guide

6.2. Source Interfaces

The following tables list the port interfaces of the source.
Table 21.  HDMI Source Reset Interface N is the number of pixels per clock.
Port Type Clock Domain Port Direction Description
Reset — reset Input Main asynchronous reset input.
Reset — reset_vid Input Reset input for the video domain.
Table 22.  HDMI Source Clock Interface N is the number of pixels per clock.
Port Type Clock Domain Port Direction Description
Clock — vid_clk Input

Video data clock input.

The vid_clk frequency can be a fixed clock frequency. Intel recommends to use 300 MHz for the vid_clk.

  • vid_clk runs at the maximum frequency across all resolutions and FRL rates.
  • The video data is qualified by the vid_valid signal.
  • vid_clk can be asynchronous to ls_clk and frl_clk.
Clock — tx_clk Input

Transceiver recovered clock. Connect this signal to the output clock of the TX transceiver output clock.

Clock — audio_clk Input

Audio clock input. Connect this signal to vid_clk by qualifying the slower frequency of audio_data with audio_de.

If you connect this signal to a clock at actual audio sample frequency, you must tie audio_de to 1.

For audio channels greater than 8, do not drive audio_clk at actual audio sample clock; instead drive audio_clk with vid_clk and qualify audio_data with audio_de.

Note: Applicable only when you turn on the Support auxiliary and Support audio parameters.
Clock — mgmt_clk Input

Free-running system clock input (100 MHz). This clock connects to the I2C controller and HPD debouncing logic.

Note: This signal is not available if you turn off the Include I2C parameter.
Table 23.  HDMI Source Video Data Port Interface N is the number of pixels per clock.
Port Type Clock Domain Port Direction Description
Conduit vid_clk vid_data[N*48-1:0] Input

Video 48-bit pixel data input port. For N pixels per clock, this port accepts N 48-bit pixels per clock.

Conduit vid_clk vid_de[N-1:0] Input Video data enable input that indicates active picture region.
Conduit vid_clk vid_hsync[N-1:0] Input Video horizontal sync input.
Conduit vid_clk vid_vsync[N-1:0] Input Video vertical sync input.
Conduit vid_clk vid_ready Output

Indicates if the TX core is ready to process new data. When vid_ready is asserted, the TX core is ready to process new data.

vid_ready is always high for 8 bits per component (BPC). This signal toggles for different color depths.

  • For 10 bpc, vid_ready is high for 4 out of 5 clock cycles.
  • For 12 bpc, vid_ready is high for 2 out of 3 clock cycles.
  • For 16 bpc, vid_ready is high for 1 out of 2 clock cycles.
  • Refer to Source Deep Color Implementation for more details.
Conduit vid_clk vid_valid Input

Indicates if the video data is valid. When vid_clk is running at the actual pixel clock, this signal should always be asserted.

When you generate the video data at a frequency higher than the actual pixel clock, use vid_valid to qualify the validity of the video data. vid_valid and vid_clk guarantee the exact pixel clock rate.

Refer to Valid Video Data for more details.

Conduit vid_clk vid_overflow Output

Reserved for FRL mode.

Table 24.  HDMI Source Data Port Interface N is the number of pixels per clock.
Port Type Clock Domain Port Direction Description
Conduit

tx_clk

out_b[transceiver width-1:0] Output

When in TMDS mode, this signal is TMDS encoded blue channel (0) output.

Transceiver width is configured to 40 bits.

Note: Only the 20 bits from the least significant bits are used.
Conduit

tx_clk

out_g[transceiver width-1:0] Output

When in TMDS mode, this signal is TMDS encoded green channel (1) output.

Transceiver width is configured to 40 bits.

Note: Only the 20 bits from the least significant bits are used.
Conduit

tx_clk

out_r[transceiver width-1:0] Output

When in TMDS mode, this signal is TMDS encoded red channel (2) output.

Transceiver width is configured to 40 bits.

Note: Only the 20 bits from the least significant bits are used.
Conduit tx_clk out_c[transceiver width-1:0] Output

When in TMDS mode, this signal is TMDS encoded clock channel (3) output.

Transceiver width is configured to 40 bits.

Note: Only the 20 bits from the least significant bits are used.
Conduit - in_lock Input

When asserted, the HDMI TX core begins to operate.

Synchronize this signal to the same clock domain as reset port.

Table 25.  HDMI Source Encoder Control Port Interface N is the number of pixels per clock.
Port Type Clock Domain Port Direction Description
Conduit tx_clk mode Input Encoding mode input.
  • 0: DVI
  • 1: HDMI
Conduit tx_clk tmds_bit_clock_ratio Input

Indicates if TMDS Bit Rate is greater than 3.4 Gbps in TMDS mode.

  • 0: (TMDS Bit Rate) / (TMDS Clock Rate) ratio is 10
  • 1 = (TMDS Bit Rate) / (TMDS Clock Rate) ratio is 40
Conduit tx_clk scrambler_enable Input

Enables scrambling.

  • 0: Instructs the source device not to perform scrambling
  • 1: Instructs the source device to perform scrambling
Conduit tx_clk ctrl[N*6-1:0] Input DVI control side-band inputs to override the necessary control and synchronization data in the green and red channels.
Bit-Field n=0,1.....N-1

n*6+5

CTL3

n*6+4

CTL2

n*6+3

CTL1

n*6+2

CTL0

n*6+1

Reserved (0)

n*6

Reserved (0)

Table 26.  HDMI Source Auxiliary Data Port Interface N is the number of pixels per clock.
Port Type Clock Domain Port Direction Description
Applicable only when you enable Support auxiliary parameter 2
Conduit aux_clk aux_ready Output Auxiliary data channel ready output. Asserted high to indicate that the core is ready to accept data.
Conduit aux_clk aux_valid Input Auxiliary data channel valid input to qualify the data.
Conduit aux_clk aux_data[71:0] Input Auxiliary data channel data input.

For information about the bit-fields, refer to Auxiliary Packet Encoder Input.

Conduit aux_clk aux_sop Input Auxiliary data channel start-of-packet input to mark the beginning of a packet.
Conduit aux_clk aux_eop Input Auxiliary data channel end-of-packet input to mark the end of a packet.
Table 27.  HDMI Source Auxiliary Control Port Interface N is the number of pixels per clock.
Port Type Clock Domain Port Direction Description
Applicable only when you enable Support auxiliary parameter2
Conduit aux_clk gcp[5:0] Input General Control Packet user input.

For information about the bit-fields, refer to Source GCP Bit-Fields.

Conduit aux_clk

info_avi[122:0]

Input Auxiliary Video Information InfoFrame user input.

For information about the bit-fields, refer to Source Auxiliary Video Information (AVI) InfoFrame.

Conduit aux_clk info_vsi[61:0] Input Vendor Specific Information InfoFrame user input.
For information about the bit-fields, refer to Source HDMI Vendor Specific InfoFrame Bit-Fields.
Table 28.  HDMI Source Auxiliary Audio Port Interface N is the number of pixels per clock.
Port Type Clock Domain Port Direction Description
Applicable only when you enable Support auxiliary and Support audio parameters2
Conduit audio_clk audio_CTS[19:0] Input Audio CTS value input.
Conduit audio_clk audio_N[19:0] Input Audio N value input.
Conduit audio_clk audio_data[255:0] Input Audio data input.

For audio channel values, refer to Audio Channels.

Conduit audio_clk audio_de Input Audio data valid input.
Conduit audio_clk audio_mute Input Audio mute input. No audio will be transmitted when this signal is asserted high.
Conduit aux_clk audio_info_ai[48:0] Input Audio InfoFrame user input.
Note: If you provide audio_info_ai [48:0] using audio_clk with actual audio sample frequency, you must synchronize the clock domain to ls_clk externally.

For information about the bit-fields, refer to Source Audio InfoFrame Bundle Bit-Fields.

Conduit aux_clk audio_metadata[165:0] Input Carries additional information related to 3D audio and MST audio.
Note: If you provide audio_metadata [165:0] using audio_clk with actual audio sample frequency, you must synchronize the clock domain to ls_clk externally.

For information about the bit-fields, refer to Audio Metadata Bundle Bit-Fields for Packet Header and Control, Audio Metadata Bundle Bit-Fields for Packet Content when 3D_AUDIO=1, and Audio Metadata Bundle Bit-Fields for Packet Content when 3D_AUDIO=0.

Conduit audio_clk audio_format[4:0] Input Controls the transmission of the 3D audio and indicates the audio format to be transmitted.
Bit-Field Description
4 Assert to indicate the first 8 channels of each 3D audio sample.
3:0

For information about the bit-fields, refer to Definition of the Supported audio_format[3:0].

Table 29.  HDMI Source PHY Interface Control Port Interface N is the number of pixels per clock.
Port Type Clock Domain Port Direction Description
Conduit tx_clk os[1:0] Input
Oversampling control signal to control the oversampling factor.
  • 1: 2x oversampling: Send this when you are transmitting TMDS rate between 1 Gb/s < rate ≤ 6 Gb/s
  • 2: 8x oversampling: Send this when you are transmitting TMDS rate ≤ 1 Gb/s
Table 30.  HDMI Source Hot Plug Detect Interface N is the number of pixels per clock.
Port Type Clock Domain Port Direction Description
Conduit — tx_hpd Input Detects the Hot Plug Detect (HPD) status. This signal should be driven with the same signal to the HPD pin on the HDMI connector.
mgmt_clk tx_hpd_req Output The core asserts the tx_hpd_req signal if the tx_hpd signal holds for more than 100 milliseconds, indicating a valid HPD. The tx_hpd_req signal deasserts if the tx_hpd signal is not detected.
Table 31.  HDMI Source I2C Controller Interface Port Interface N is the number of pixels per clock.
Port Type Clock Domain Port Direction Description
Conduit — i2c_scl Inout The SCL signal from the I2C bus on the HDMI connector.
Note: This signal is not available if you turn off the Include I2C or Include I2C Pads parameter.
Conduit — i2c_sda Inout The SDA signal from the I2C bus on the HDMI connector.
Note: This signal is not available if you turn off the Include I2C or Include I2C Pads parameter.
Conduit — i2c_scl_in Input The SCL input signal from the HDMI connector I2C tri-statable I/O pad.
Note: This signal is only available when you turn off the Include I2C Pads parameter.
Conduit — i2c_scl_oe Output

The SCL output enable signal to the HDMI connector I2C tri-stateable I/O pad.

1: SCL pulled low

0: Output buffer tri-stated and SCL externally pulled high
Note: This signal is only available when you turn off the Include I2C Pads parameter.
Conduit — i2c_sda_in Input The SDA input signal from the HDMI connector I2C tri-stateable I/O pad.
Note: This signal is only available when you turn off the Include I2C Pads parameter.
Conduit — i2c_sda_oe Output

The SDA output enable signal to the HDMI connector I2C tri-stateable I/O pad.

1: SDA pulled low

0: Output buffer tri-stated and SDA externally pulled high
Note: This signal is only available when you turn off the Include I2C Pads parameter.
Avalon® memory-mapped interface mgmt_clk i2c_master_address[3:0] Input The Avalon® memory-mapped interface signals to the I2C controller. Connect these signals to an Avalon® memory-mapped host such as the Nios® processor to perform read and write operations to the EDID block.
Note: These signals are not available if you turn off the Include I2C parameter.
Avalon® memory-mapped interface mgmt_clk i2c_master_write Input
Avalon® memory-mapped interface mgmt_clk i2c_master_read Input
Avalon® memory-mapped interface mgmt_clk i2c_master_writedata[31:0] Input
Avalon® memory-mapped interface mgmt_clk i2c_master_readdata[31:0] Output
Table 32.  out_c Value for TMDS Bit Rate Less than 3.4 Gbps TMDS_Bit_clock_Ratio = 0 and out_c value is constant.
N out_c Value
1 10'b1111100000
2 20'b1111100000_1111100000
4 40'b1111100000_1111100000 1111100000_1111100000
Table 33.  out_c Value for TMDS Bit Rate Greater than 3.4 Gbps in TMDS Mode TMDS_Bit_clock_Ratio = 1 and out_c value is repeated indefinitely.
N out_c Value
t t+1 t+2 t+3
1 10’h000 10’h000 10’h3ff 10’h3ff
2 20’h00000 20’hfffff 20'h00000 20’hfffff
4 40’hfffff 00000 40’hfffff 00000 40’hfffff 00000 40’hfffff 00000
Table 34.  Audio Channels
Bit-Field Audio Channel
LPCM and 3D Audio (LPCM) MST Audio (LPCM)
255:224 8 or 16 or 24 or 32

Stream 4 right channel

223:192 7 or 15 or 23 or 31

Stream 4 left channel

191:160 6 or 14 or 22 or 30

Stream 3 right channel

159:128 5 or 13 or 21 or 29

Stream 3 left channel

127:96 4 or 12 or 20 or 28

Stream 2 right channel

95:64 3 or 11 or 19 or 27

Stream 2 left channel

63:32 2 or 10 or 18 or 26

Stream 1 right channel

31:0 1 or 9 or 17 or 25

Stream 1 left channel

2

aux_clk = vid_clk

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