GTS HDMI Intel® FPGA IP Design Example User Guide

ID 823528
Date 3/07/2025
Public
Document Table of Contents

4. Simulation Testbench

The HDMI testbench simulates a serial loopback design from a TX instance to an RX instance. Internal video pattern generator, audio sample generator, sideband data generator, and auxiliary data generator modules drive the HDMI TX instance and the serial output from the TX instance connects to the RX instance in the testbench.

The simulation support two different mode of simulation:

  • HDMI IP Core with Integrated Transceiver (with dual simplex)
  • HDMI IP Core without Integrated Transceiver (non Integrated Transceiver)
Table 32.  Parameter Setting for Different Variants

Design Variant

IP Parameter

HDMI Wrapper

Transceiver Data Rate

Clocked Video

With Integrated Transceiver

HDMI and Transceiver

5.94G, 2.97G, 1.485G, 0.7425G, 0.27G

Without Integrated Transceiver

HDMI Only

Not Applicable

Figure 14. Design Simulation Flow
  1. Go to the desired simulation folder.
  2. Run the simulation script for the supported simulator of your choice. The script compiles and runs the testbench in the simulator.
  3. Analyze the results.
Table 33.  Steps to Run Simulation
Simulator Working Directory Instructions
Riviera-PRO* /simulation/aldec
In the command line, type
vsim -c -do aldec.do
ModelSim* /simulation/mentor
In the command line, type
vsim -c -do mentor.do
VCS* MX /simulation/synopsys/vcsmx
In the command line, type
source vcsmx_sim.sh
Xcelium* Parallel /simulation/xcelium In the command line, type
source xcelium_sim.sh