GTS HDMI Intel® FPGA IP Design Example User Guide

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ID 823528
Date 3/07/2025
Public
Document Table of Contents
Document Table of Contents x
1. GTS HDMI Intel® FPGA IP Design Example Quick Start Guide for Agilex™ 5 Devices 2. Dual Simplex Mode with the HDMI Simplex IP 3. Design Example Variants 4. Simulation Testbench 5. Document Revision History for the GTS HDMI Intel® FPGA IP Design Example User Guide for Agilex™ 5 Devices
1. GTS HDMI Intel® FPGA IP Design Example Quick Start Guide for Agilex™ 5 Devices x
1.1. Design Description 1.2. Supported HDMI Features 1.3. Software Requirements 1.4. Generating the Design 1.5. Simulating the Design
2. Dual Simplex Mode with the HDMI Simplex IP x
2.1. HDMI RX with Integrated Transceiver 2.2. HDMI TX with Integrated Transceiver 2.3. Requirement for Dual Simplex 2.4. Creating Dual Simplex Groups
2.1. HDMI RX with Integrated Transceiver x
2.1.1. HDMI RX Parameters for Integrated Transceiver Mode
2.2. HDMI TX with Integrated Transceiver x
2.2.1. HDMI TX Parameters for Integrated Transceiver Mode
3. Design Example Variants x
3.1. Agilex™ 5 HDMI RX-TX Retransmit with Integrated Transceiver Design Example Variant 3.2. Agilex™ 5 HDMI RX-TX Retransmit Without Integrated Transceiver Design Example Variant
3.1. Agilex™ 5 HDMI RX-TX Retransmit with Integrated Transceiver Design Example Variant x
3.1.1. HDMI RX-TX Retransmit With Integrated Transceiver Design Parameters 3.1.2. Integrated Transceiver With Dual Simplex Block Diagram 3.1.3. Integrated Transceiver Without Dual Simplex Block Diagram 3.1.4. Agilex™ 5 HDMI RX-TX Retransmit With Integrated Transceiver Design Example Top Level Common Blocks 3.1.5. Agilex™ 5 HDMI RX-TX Retransmit With Integrated Transceiver Design Example Interface Signals
3.2. Agilex™ 5 HDMI RX-TX Retransmit Without Integrated Transceiver Design Example Variant x
3.2.1. HDMI RX-TX Retransmit Without Integrated Transceiver Design Parameters 3.2.2. Non-Integrated Transceiver With Dual Simplex Block Diagram 3.2.3. Non-Integrated Transceiver Without Dual Simplex block diagram 3.2.4. Agilex™ 5 HDMI RX-TX Retransmit Without Integrated Transceiver Design Example Top Level Common Blocks 3.2.5. Agilex™ 5 HDMI RX-TX Retransmit Without Integrated Transceiver Design Example Interface Signals
4. Simulation Testbench x
4.1. Non-Integrated Transceiver Simulation Testbench 4.2. Integrated Transceiver (With Dual Simplex) Simulation Testbench 4.3. Simulation Testbench Parameters 4.4. Simulation Time Benchmark
1. GTS HDMI Intel® FPGA IP Design Example Quick Start Guide for Agilex™ 5 Devices
2. Dual Simplex Mode with the HDMI Simplex IP
3. Design Example Variants
4. Simulation Testbench
5. Document Revision History for the GTS HDMI Intel® FPGA IP Design Example User Guide for Agilex™ 5 Devices

3. Design Example Variants

The hardware design example supports both the Integrated Transceiver and the non-Integrated Transceiver modes of the GTS HDMI Intel® FPGA IP.

For designs with Integrated Transceiver, the transceiver IP is located inside the HDMI IP. All the settings for the transceiver handled by HDMI IP.

For designs without Integrated Transceiver, the transceiver lP is located outside of the HDMI IP. The transceiver IP is instantiated at the top level module. For this mode, you can change the transceiver settings based on your needs.

Table 7.  Parameter setting for different variants

Design Variant

Parameter

HDMI Wrapper

Transceiver Data Rate

Active Video Protocol

Clocked Video

With Integrated Transceiver

HDMI and Transceiver

5.94G, 2.97G, 1.485G, 0.7425G, 0.27G

None

Without Integrated Transceiver

HDMI Only

Not Applicable

None
Table 8.  Resource Utilization for the Variant With Integrated Transceiver

Direction

HDMI Wrapper

Active Video Protocol

ALM

Logic Registers

Memory

Bits

M10K or M20K

HDMI RX

HDMI and Transceiver

None

4995

8956

58256

16

HDMI TX

HDMI and Transceiver

None

4388

9816

75712

14

Dual Simplex Group (HDMI RX + HDMI TX)

HDMI and Transceiver

None

11922

21087

215888

34

Full Design Example

HDMI and Transceiver

None

16407

25989

4433072

299
Table 9.  Resource Utilization for the Variant Without Integrated Transceiver

Direction

HDMI Wrapper

Active Video Protocol

ALM

Logic Registers

Memory

Bits

M10K or M20K

HDMI RX

HDMI Only

None

4815

9159

42896

13

HDMI TX

HDMI Only

None

4051

9193

34752

10

Full Design Example

HDMI Only

None

16275

26653

4433072

299

Section Content
Agilex 5 HDMI RX-TX Retransmit with Integrated Transceiver Design Example Variant
Agilex 5 HDMI RX-TX Retransmit Without Integrated Transceiver Design Example Variant

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