GTS HDMI Intel® FPGA IP Design Example User Guide

Download PDF
ID 823528
Date 3/07/2025
Public
Document Table of Contents
Document Table of Contents x
1. GTS HDMI Intel® FPGA IP Design Example Quick Start Guide for Agilex™ 5 Devices 2. Dual Simplex Mode with the HDMI Simplex IP 3. Design Example Variants 4. Simulation Testbench 5. Document Revision History for the GTS HDMI Intel® FPGA IP Design Example User Guide for Agilex™ 5 Devices
1. GTS HDMI Intel® FPGA IP Design Example Quick Start Guide for Agilex™ 5 Devices x
1.1. Design Description 1.2. Supported HDMI Features 1.3. Software Requirements 1.4. Generating the Design 1.5. Simulating the Design
2. Dual Simplex Mode with the HDMI Simplex IP x
2.1. HDMI RX with Integrated Transceiver 2.2. HDMI TX with Integrated Transceiver 2.3. Requirement for Dual Simplex 2.4. Creating Dual Simplex Groups
2.1. HDMI RX with Integrated Transceiver x
2.1.1. HDMI RX Parameters for Integrated Transceiver Mode
2.2. HDMI TX with Integrated Transceiver x
2.2.1. HDMI TX Parameters for Integrated Transceiver Mode
3. Design Example Variants x
3.1. Agilex™ 5 HDMI RX-TX Retransmit with Integrated Transceiver Design Example Variant 3.2. Agilex™ 5 HDMI RX-TX Retransmit Without Integrated Transceiver Design Example Variant
3.1. Agilex™ 5 HDMI RX-TX Retransmit with Integrated Transceiver Design Example Variant x
3.1.1. HDMI RX-TX Retransmit With Integrated Transceiver Design Parameters 3.1.2. Integrated Transceiver With Dual Simplex Block Diagram 3.1.3. Integrated Transceiver Without Dual Simplex Block Diagram 3.1.4. Agilex™ 5 HDMI RX-TX Retransmit With Integrated Transceiver Design Example Top Level Common Blocks 3.1.5. Agilex™ 5 HDMI RX-TX Retransmit With Integrated Transceiver Design Example Interface Signals
3.2. Agilex™ 5 HDMI RX-TX Retransmit Without Integrated Transceiver Design Example Variant x
3.2.1. HDMI RX-TX Retransmit Without Integrated Transceiver Design Parameters 3.2.2. Non-Integrated Transceiver With Dual Simplex Block Diagram 3.2.3. Non-Integrated Transceiver Without Dual Simplex block diagram 3.2.4. Agilex™ 5 HDMI RX-TX Retransmit Without Integrated Transceiver Design Example Top Level Common Blocks 3.2.5. Agilex™ 5 HDMI RX-TX Retransmit Without Integrated Transceiver Design Example Interface Signals
4. Simulation Testbench x
4.1. Non-Integrated Transceiver Simulation Testbench 4.2. Integrated Transceiver (With Dual Simplex) Simulation Testbench 4.3. Simulation Testbench Parameters 4.4. Simulation Time Benchmark
1. GTS HDMI Intel® FPGA IP Design Example Quick Start Guide for Agilex™ 5 Devices
2. Dual Simplex Mode with the HDMI Simplex IP
3. Design Example Variants
4. Simulation Testbench
5. Document Revision History for the GTS HDMI Intel® FPGA IP Design Example User Guide for Agilex™ 5 Devices

3.1.1. HDMI RX-TX Retransmit With Integrated Transceiver Design Parameters

Use the GTS HDMI Intel FPGA IP parameter editor to customize the design example. Most of the design parameters are available in the IP and Design Example tab of the GTS HDMI Intel FPGA IP parameter editor.

Table 10.  HDMI RX Parameters for Integrated Transceiver Mode

Parameter

Value

Description

DIRECTION

Receiver

Determines the selection for HDMI Simplex RTL

SUPPORT DEEP COLOR

0: No deep color

1: Deep color

Determines if the core can encode deep color formats.

SUPPORT AUXILIARY

0: No AUX

1: AUX

Determines if the auxiliary channel encoding is included.

SUPPORT AUDIO

0: No audio

1: Audio

Determines if the core can encode audio.

PIXELS PER CLOCK

2

Supports 2 symbols per clock for Agilex™ 5 devices.

INCLUDE I2C MASTER/SLAVE

0: Disable

1: Enable

Determines if the I2C target block is included.

INCLUDE I2C IO PADS

0: Disable

1: Enable

Determines if the I/O buffer for the I2C signals is included.

Takes effect only if INCLUDE I2C MASTER/SLAVE parameter is enabled.

INCLUDE EDID RAM

0: Disable

1: Enable

Determines if the EDID RAM block is included.

EDID_RAM_ADDR_WIDTH

8 (Default Value)

Log base 2 of the EDID RAM size.

HDMI21_VARIANT

0: TMDS only

Determines the selection of HDMI variant.

WRAPPER OPTION

1: HDMI and Transceiver

Determines the Transceiver instantiated inside HDMI IP

TRANSCEIVER DATA RATE

0: 5.94G

1: 2.97G

2: 1.485G

3: 0.7425G

4: 0.27G
Determines Static Transceiver Data Rate based on the resolution:
  • 5.94G (VIC97: 4kp60)
  • 2.97G (VIC95: 4kp30)
  • 1.485G (VIC16: 1080p60)
  • 0.7425G (VIC4: 720p60)
  • 0.27G (VIC2: 480p60)
Table 11.  HDMI TX Parameters for Integrated Transceiver Mode

Parameter

Value

Description

DIRECTION

Transmitter

Determines the selection for HDMI Simplex RTL

SUPPORT DEEP COLOR

0: No deep color

1: Deep color

Determines if the core can encode deep color formats.

SUPPORT AUXILIARY

0: No AUX

1: AUX

Determines if the auxiliary channel encoding is included.

SUPPORT AUDIO

0: No audio

1: Audio

Determines if the core can encode audio.

PIXELS PER CLOCK

2

Supports 2 symbols per clock for Agilex™ 5 devices.

INCLUDE I2C MASTER/SLAVE

0: Disable

1: Enable

Determines if the I2C target block is included.
INCLUDE I2C IO PADS

0: Disable

1: Enable

 Determines if the I/O buffer for the I2C signals is included.

Takes effect only if INCLUDE I2C MASTER/SLAVE parameter is enabled.

HDMI21_VARIANT

0: TMDS only

Determines the selection of HDMI variant.

WRAPPER OPTION

1: HDMI and Transceiver

Determines the Transceiver instantiated inside HDMI IP

TRANSCEIVER DATA RATE

0: 5.94G

1: 2.97G

2: 1.485G

3: 0.7425G

4: 0.27G
Determines Static Transceiver Data Rate based on the resolution:
  • 5.94G (VIC97: 4kp60)
  • 2.97G (VIC95: 4kp30)
  • 1.485G (VIC16: 1080p60)
  • 0.7425G (VIC4: 720p60)
  • 0.27G (VIC2: 480p60)
Table 12.  Design Example Parameters

Parameter

Value

Description

Available Design Example

Select Design

1: Agilex 5 HDMI RX-TX Retransmit with integrated Transceiver and Dual Simplex

Select the design example to be generated. The generated design example has pre-configured parameter settings. It does not follow user settings.

Select Daughter Card Revision

0: Bitec* HDMI FMC 2.1 daughter card (Revision 9)

1: No Daughter Card

Select available HDMI daughter card for Design Example generation.

Design Example Files

Simulation

On, Off

Turn on this option to generate the necessary files for the simulation testbench.

Note: Design example simulation is not supported if Include I2C is selected.

Note: Design example simulation is not supported if Without Dual Simplex option is selected.

Synthesis

On, Off

Turn on this option to generate the necessary files for Intel Quartus Prime compilation and hardware demonstration.

Generated HDL Format

Generate File Format

Verilog, VHDL

Select your preferred HDL format for the generated design example fileset.

Note: This option only determines the format for the generated top level IP files. All other files (e.g. example testbenches and top level files for hardware demonstration) are in Verilog HDL format.

Target Development Kit

Select Board

No Development Kit

Agilex™ 5 FPGA Development Kit

Select the board for the targeted design example.
  • No Development Kit

    This option excludes all hardware aspects for the design example. The IP core sets all pin assignments to virtual pins.

  • Agilex™ 5 FPGA Development Kit

    This option automatically selects the project's target device to match the device on this development kit (A5ED065BB32AE6SR0). You may change the target device using the Change Target Device parameter if your board revision has a different device variant. The IP core sets all pin assignments according to the development kit.

Target Device

Change Target Device

On, Off

Turn on this option and select the preferred device variant for the development kit.
Figure 6. GUI Parameter SettingsWhen you select HDMI and Transceiver in the Wrapper Option field, the Quartus® Prime IP Catalog GUI shows additional fields. These additional fields are highlighted here by red boxes.
Level Two Title