GTS HDMI Intel® FPGA IP Design Example User Guide

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ID 823528
Date 3/07/2025
Public
Document Table of Contents
Document Table of Contents x
1. GTS HDMI Intel® FPGA IP Design Example Quick Start Guide for Agilex™ 5 Devices 2. Dual Simplex Mode with the HDMI Simplex IP 3. Design Example Variants 4. Simulation Testbench 5. Document Revision History for the GTS HDMI Intel® FPGA IP Design Example User Guide for Agilex™ 5 Devices
1. GTS HDMI Intel® FPGA IP Design Example Quick Start Guide for Agilex™ 5 Devices x
1.1. Design Description 1.2. Supported HDMI Features 1.3. Software Requirements 1.4. Generating the Design 1.5. Simulating the Design
2. Dual Simplex Mode with the HDMI Simplex IP x
2.1. HDMI RX with Integrated Transceiver 2.2. HDMI TX with Integrated Transceiver 2.3. Requirement for Dual Simplex 2.4. Creating Dual Simplex Groups
2.1. HDMI RX with Integrated Transceiver x
2.1.1. HDMI RX Parameters for Integrated Transceiver Mode
2.2. HDMI TX with Integrated Transceiver x
2.2.1. HDMI TX Parameters for Integrated Transceiver Mode
3. Design Example Variants x
3.1. Agilex™ 5 HDMI RX-TX Retransmit with Integrated Transceiver Design Example Variant 3.2. Agilex™ 5 HDMI RX-TX Retransmit Without Integrated Transceiver Design Example Variant
3.1. Agilex™ 5 HDMI RX-TX Retransmit with Integrated Transceiver Design Example Variant x
3.1.1. HDMI RX-TX Retransmit With Integrated Transceiver Design Parameters 3.1.2. Integrated Transceiver With Dual Simplex Block Diagram 3.1.3. Integrated Transceiver Without Dual Simplex Block Diagram 3.1.4. Agilex™ 5 HDMI RX-TX Retransmit With Integrated Transceiver Design Example Top Level Common Blocks 3.1.5. Agilex™ 5 HDMI RX-TX Retransmit With Integrated Transceiver Design Example Interface Signals
3.2. Agilex™ 5 HDMI RX-TX Retransmit Without Integrated Transceiver Design Example Variant x
3.2.1. HDMI RX-TX Retransmit Without Integrated Transceiver Design Parameters 3.2.2. Non-Integrated Transceiver With Dual Simplex Block Diagram 3.2.3. Non-Integrated Transceiver Without Dual Simplex block diagram 3.2.4. Agilex™ 5 HDMI RX-TX Retransmit Without Integrated Transceiver Design Example Top Level Common Blocks 3.2.5. Agilex™ 5 HDMI RX-TX Retransmit Without Integrated Transceiver Design Example Interface Signals
4. Simulation Testbench x
4.1. Non-Integrated Transceiver Simulation Testbench 4.2. Integrated Transceiver (With Dual Simplex) Simulation Testbench 4.3. Simulation Testbench Parameters 4.4. Simulation Time Benchmark
1. GTS HDMI Intel® FPGA IP Design Example Quick Start Guide for Agilex™ 5 Devices
2. Dual Simplex Mode with the HDMI Simplex IP
3. Design Example Variants
4. Simulation Testbench
5. Document Revision History for the GTS HDMI Intel® FPGA IP Design Example User Guide for Agilex™ 5 Devices

1.2. Supported HDMI Features

HDMI support for Agilex™ 5 devices is available in Quartus® Prime version 24.3 or later. HDMI features are planned to be supported in stages. The following table shows current state of HDMI feature support for Agilex™ 5 devices:
Table 2.  HDMI Feature Support in Quartus® Prime for Agilex™ 5 Devices
Design Variant Simulation Compilation Timing Hardware (Static) Hardware (Multirate)
Type Integrated Transceiver Dual Simplex
Clocked Video Yes Yes Supported as of Version 24.3 Supported as of Version 24.3 Supported as of Version 24.3 Planned for a future version Planned for a future version
Yes No Supported as of Version 24.3 Supported as of Version 24.3 Supported as of Version 24.3 Not available Not available
No Yes Supported as of Version 24.3 Supported as of Version 24.3 Supported as of Version 24.3 Planned for a future version Planned for a future version
No No Supported as of Version 24.3 Supported as of Version 24.3 Supported as of Version 24.3 Not available Not available
VVP Full1 Not available Not available Not available Not available Not available
Table 3.  Simulator Tools Support in Quartus® Prime for Agilex™ 5 Devices
Design Variant Aldec* Riviera-PRO* Questa*-Intel® FPGA Edition Siemens* EDA Questa* Advanced Simulator VCS* VCS* MX Xcelium*
Without Integrated Transceiver Not supported 24.3 24.3 Not supported 24.3 24.3
With Integrated Transceiver (with DS) Not supported 24.3 24.3 Not supported 24.3 24.3
1 VVP Full design variant support is dependent on the Platform Designer support for Dual Simplex Tools.
Level Two Title