GTS HDMI Intel® FPGA IP Design Example User Guide

ID 823528
Date 3/07/2025
Public
Document Table of Contents

2.1.1. HDMI RX Parameters for Integrated Transceiver Mode

Table 5.  HDMI RX Parameters for Integrated Transceiver Mode

Parameter

Value

Description

DIRECTION

Receiver

Determines the selection for HDMI Simplex RTL

SUPPORT DEEP COLOR

0: No deep color

1: Deep color

Determines if the core can encode deep color formats.

SUPPORT AUXILIARY

0: No AUX

1: AUX

Determines if the auxiliary channel encoding is included.

SUPPORT AUDIO

0: No audio

1: Audio

Determines if the core can encode audio.

PIXELS PER CLOCK

2

Supports 2 symbols per clock for Agilex™ 5 devices.

INCLUDE I2C MASTER/SLAVE

0: Disable

1: Enable

Determines if the I2C target block is included.

INCLUDE I2C IO PADS

0: Disable

1: Enable

Determines if the I/O buffer for the I2C signals is included.

Takes effect only if INCLUDE I2C MASTER/SLAVE parameter is enabled.

INCLUDE EDID RAM

0: Disable

1: Enable

Determines if the EDID RAM block is included.

EDID_RAM_ADDR_WIDTH

8 (Default Value)

Log base 2 of the EDID RAM size.

HDMI21_VARIANT

0: TMDS only

Determines the selection of HDMI variant.

WRAPPER OPTION

1: HDMI and Transceiver

Determines the Transceiver instantiated inside HDMI IP

TRANSCEIVER DATA RATE

0: 5.94G

1: 2.97G

2: 1.485G

3: 0.7425G

4: 0.27G

Determines Static Transceiver Data Rate based on the resolution:
  • 5.94G (VIC97: 4kp60)
  • 2.97G (VIC95: 4kp30)
  • 1.485G (VIC16: 1080p60)
  • 0.7425G (VIC4: 720p60)
  • 0.27G (VIC2: 480p60)