GTS HDMI Intel® FPGA IP Design Example User Guide

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ID 823528
Date 3/07/2025
Public
Document Table of Contents
Document Table of Contents x
1. GTS HDMI Intel® FPGA IP Design Example Quick Start Guide for Agilex™ 5 Devices 2. Dual Simplex Mode with the HDMI Simplex IP 3. Design Example Variants 4. Simulation Testbench 5. Document Revision History for the GTS HDMI Intel® FPGA IP Design Example User Guide for Agilex™ 5 Devices
1. GTS HDMI Intel® FPGA IP Design Example Quick Start Guide for Agilex™ 5 Devices x
1.1. Design Description 1.2. Supported HDMI Features 1.3. Software Requirements 1.4. Generating the Design 1.5. Simulating the Design
2. Dual Simplex Mode with the HDMI Simplex IP x
2.1. HDMI RX with Integrated Transceiver 2.2. HDMI TX with Integrated Transceiver 2.3. Requirement for Dual Simplex 2.4. Creating Dual Simplex Groups
2.1. HDMI RX with Integrated Transceiver x
2.1.1. HDMI RX Parameters for Integrated Transceiver Mode
2.2. HDMI TX with Integrated Transceiver x
2.2.1. HDMI TX Parameters for Integrated Transceiver Mode
3. Design Example Variants x
3.1. Agilex™ 5 HDMI RX-TX Retransmit with Integrated Transceiver Design Example Variant 3.2. Agilex™ 5 HDMI RX-TX Retransmit Without Integrated Transceiver Design Example Variant
3.1. Agilex™ 5 HDMI RX-TX Retransmit with Integrated Transceiver Design Example Variant x
3.1.1. HDMI RX-TX Retransmit With Integrated Transceiver Design Parameters 3.1.2. Integrated Transceiver With Dual Simplex Block Diagram 3.1.3. Integrated Transceiver Without Dual Simplex Block Diagram 3.1.4. Agilex™ 5 HDMI RX-TX Retransmit With Integrated Transceiver Design Example Top Level Common Blocks 3.1.5. Agilex™ 5 HDMI RX-TX Retransmit With Integrated Transceiver Design Example Interface Signals
3.2. Agilex™ 5 HDMI RX-TX Retransmit Without Integrated Transceiver Design Example Variant x
3.2.1. HDMI RX-TX Retransmit Without Integrated Transceiver Design Parameters 3.2.2. Non-Integrated Transceiver With Dual Simplex Block Diagram 3.2.3. Non-Integrated Transceiver Without Dual Simplex block diagram 3.2.4. Agilex™ 5 HDMI RX-TX Retransmit Without Integrated Transceiver Design Example Top Level Common Blocks 3.2.5. Agilex™ 5 HDMI RX-TX Retransmit Without Integrated Transceiver Design Example Interface Signals
4. Simulation Testbench x
4.1. Non-Integrated Transceiver Simulation Testbench 4.2. Integrated Transceiver (With Dual Simplex) Simulation Testbench 4.3. Simulation Testbench Parameters 4.4. Simulation Time Benchmark
1. GTS HDMI Intel® FPGA IP Design Example Quick Start Guide for Agilex™ 5 Devices
2. Dual Simplex Mode with the HDMI Simplex IP
3. Design Example Variants
4. Simulation Testbench
5. Document Revision History for the GTS HDMI Intel® FPGA IP Design Example User Guide for Agilex™ 5 Devices

3.1.2. Integrated Transceiver With Dual Simplex Block Diagram

For Agilex™ 5 HDMI RX-TX Retransmit with integrated Transceiver with dual simplex (DS), the Transceiver IP instantiated inside the HDMI IP. The HDMI IP (RX and TX) are wrapped into a Dual Simplex Group. Both RX and TX transceiver are placed at the same channel.

The RX and TX simplex IPs are merged into a dual simplex group with the Assignment Editor. For more information about implementing dual simplex interfaces, refer to "Implementing Dual Simplex Interfaces" in the GTS Transceiver Dual Simplex Interfaces User Guide .

Figure 7. Dual Simplex Assignment Editor
Figure 8. HDMI RX-TX Retransmit Block Diagram (with Dual Simplex)
Level Two Title