RX-TX Link

The video data output and synchronization signals from HDMI RX core loop through a DCFIFO across the RX and TX video clock domains.

The auxiliary data port of the HDMI TX core controls the auxiliary data that flow through the DCFIFO through backpressure. The backpressure ensures there is no incomplete auxiliary packet on the auxiliary data port.

This block also performs external filtering:

Filters the audio data and audio clock regeneration packet from the auxiliary data stream before transmitting to the HDMI TX core auxiliary data port.

CPU Subsystem

The CPU subsystem functions as SCDC and DDC controllers, and source reconfiguration controller.

The source SCDC controller contains the I2C master controller. The I2C master controller transfers the SCDC data structure from the FPGA source to the external sink for HDMI 2.0 operation. For example, if the outgoing data stream is 6,000 Mbps, the Nios® V processor commands the I2C master controller to update the TMDS_BIT_CLOCK_RATIO and SCRAMBLER_ENABLE bits of the sink TMDS configuration register to 1.

The same I2C master also transfers the DDC data structure (E-EDID) between the HDMI source and external sink.

The Nios® V CPU acts as the reconfiguration controller for the HDMI source. The CPU relies on the periodic rate detection from the RX Reconfiguration Management module to determine if the TX requires reconfiguration. The Avalon® memory-mapped slave translator provides the interface between the Nios® V processor Avalon® memory-mapped master interface and the Avalon® memory-mapped slave interfaces of the externally instantiated HDMI source IOPLL and TX PMA Direct PHY.

IOPLL (vid_clk)

The IOPLL performs the following:

Generates the video clock. The reference clock to this IOPLL is 100 MHz clock.

Provides fix clock frequency which is 225 MHz.

System PLL Clock

This IP connects the System PLL output clock as well as the Tx PLL and Rx CDR reference clock to the PMA/FEC Direct PHY IP.

System PLL clock output shall always set to run at a higher clock frequency than the native PMA recovered clock.

For this design, the clock frequency is 700 MHz.

GTS Reset Sequencer

GTS Reset Sequencer Intel® FPGA IP ensure that only one transmitter or receiver lane undergoes reset-entry or reset-exit at a time per side of the device to comply with SiPi (Signal and Power Integrity). The GTS Reset Sequencer IP gets the requests from all the Soft Reset Controller(SRC) Lanes per side of the device and these requests will get granted one at a time in round robin.

Dual Simplex Group

Dual Simplex tools generated files. This dual simplex group only generated if Agilex 5 HDMI RX-TX Retransmit without integrated Transceiver and with Dual Simplex design was selected. This files isgenerated during “HSSI Dual Simplex IP generation flow”. This dual simplex group contains PMA Direct PHY RX and TX.

HDMI RX Top

The HDMI RX top components include the RX core top-level components, optional I2C slave and EDID RAM, DCFIFO and PHY adapter.

HDMI RX IP receives the parallel data from the Transceiver PMA Direct PHY and performs data alignment, channel deskew, TMDS decoding, auxiliary data decoding, video data decoding, audio data decoding, and descrambling.

HDMI TX Top

The HDMI TX top components include the TX core top-level components, DCFIFO, phy adapter, and the output buffer blocks.

HDMI TX IP receives video data from the top level and performs auxiliary data encoding, audio data encoding, video data encoding, scrambling, TMDS encoding or packetization.