GTS HDMI Intel® FPGA IP Design Example User Guide

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ID 823528
Date 3/07/2025
Public
Document Table of Contents
Document Table of Contents x
1. GTS HDMI Intel® FPGA IP Design Example Quick Start Guide for Agilex™ 5 Devices 2. Dual Simplex Mode with the HDMI Simplex IP 3. Design Example Variants 4. Simulation Testbench 5. Document Revision History for the GTS HDMI Intel® FPGA IP Design Example User Guide for Agilex™ 5 Devices
1. GTS HDMI Intel® FPGA IP Design Example Quick Start Guide for Agilex™ 5 Devices x
1.1. Design Description 1.2. Supported HDMI Features 1.3. Software Requirements 1.4. Generating the Design 1.5. Simulating the Design
2. Dual Simplex Mode with the HDMI Simplex IP x
2.1. HDMI RX with Integrated Transceiver 2.2. HDMI TX with Integrated Transceiver 2.3. Requirement for Dual Simplex 2.4. Creating Dual Simplex Groups
2.1. HDMI RX with Integrated Transceiver x
2.1.1. HDMI RX Parameters for Integrated Transceiver Mode
2.2. HDMI TX with Integrated Transceiver x
2.2.1. HDMI TX Parameters for Integrated Transceiver Mode
3. Design Example Variants x
3.1. Agilex™ 5 HDMI RX-TX Retransmit with Integrated Transceiver Design Example Variant 3.2. Agilex™ 5 HDMI RX-TX Retransmit Without Integrated Transceiver Design Example Variant
3.1. Agilex™ 5 HDMI RX-TX Retransmit with Integrated Transceiver Design Example Variant x
3.1.1. HDMI RX-TX Retransmit With Integrated Transceiver Design Parameters 3.1.2. Integrated Transceiver With Dual Simplex Block Diagram 3.1.3. Integrated Transceiver Without Dual Simplex Block Diagram 3.1.4. Agilex™ 5 HDMI RX-TX Retransmit With Integrated Transceiver Design Example Top Level Common Blocks 3.1.5. Agilex™ 5 HDMI RX-TX Retransmit With Integrated Transceiver Design Example Interface Signals
3.2. Agilex™ 5 HDMI RX-TX Retransmit Without Integrated Transceiver Design Example Variant x
3.2.1. HDMI RX-TX Retransmit Without Integrated Transceiver Design Parameters 3.2.2. Non-Integrated Transceiver With Dual Simplex Block Diagram 3.2.3. Non-Integrated Transceiver Without Dual Simplex block diagram 3.2.4. Agilex™ 5 HDMI RX-TX Retransmit Without Integrated Transceiver Design Example Top Level Common Blocks 3.2.5. Agilex™ 5 HDMI RX-TX Retransmit Without Integrated Transceiver Design Example Interface Signals
4. Simulation Testbench x
4.1. Non-Integrated Transceiver Simulation Testbench 4.2. Integrated Transceiver (With Dual Simplex) Simulation Testbench 4.3. Simulation Testbench Parameters 4.4. Simulation Time Benchmark
1. GTS HDMI Intel® FPGA IP Design Example Quick Start Guide for Agilex™ 5 Devices
2. Dual Simplex Mode with the HDMI Simplex IP
3. Design Example Variants
4. Simulation Testbench
5. Document Revision History for the GTS HDMI Intel® FPGA IP Design Example User Guide for Agilex™ 5 Devices

1.5. Simulating the Design

The HDMI testbench simulates a serial loopback design from a TX instance to an RX instance. Internal video pattern generator, audio sample generator, sideband data generator, and auxiliary data generator modules drive the HDMI TX instance and the serial output from the TX instance connects to the RX instance in the testbench.
Note: HDMI simulation is not supported when the Include I2C Master/Slave option is enabled in the IP tab.
Figure 3. Design Simulation Flow
  1. Go to the desired simulation folder.
  2. Run the simulation script for the supported simulator of your choice. The script compiles and runs the testbench in the simulator.
  3. Analyze the results.
    Table 4.  Steps to Run Simulation
    Simulator Working Directory Instructions
    Riviera-PRO* /simulation/aldec
    In the command line, type 
    vsim -c -do aldec.do
    ModelSim* /simulation/mentor
    In the command line, type 
    vsim -c -do mentor.do
    VCS* MX /simulation/synopsys/vcsmx
    In the command line, type 
    source vcsmx_sim.sh
    Xcelium* Parallel /simulation/xcelium In the command line, type 
    source xcelium_sim.sh
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