On-board Oscillator Signal

core_refclk_100

Input

1

100 MHz free running clock for core reference clock.

syspll_refclk0

Input

1

100 MHz free running clock for Systempll reference clock.

cpu_resetn

Input

1

Global reset.

user_pb

Input

1

Push button to control the HDMI Intel FPGA IP design functionality.

fmc_rx_p/fmc_rx_n

Input

3

HDMI RX clock, red, green, and blue data channels.

fmc_tx_p/fmc_tx/n

Output

4

HDMI TX clock, red, green, and blue data channels.

hdmi_5v_detect_n

Input

1

HDMI RX +5V power detect.

hdmi_rx_hpd

Input

1

HDMI RX hot plug detect.

hdmi_rx_i2c_sda

Input/Output

1

HDMI RX I2C SDA for DDC and SCDC.

hdmi_rx_i2c_scl

Input

1

HDMI RX I2C SCL for DDC and SCDC.

hdmi_tx_5v

Output

1

HDMI TX 5V output.

hdmi_tx_hpd_n

Input

1

HDMI TX hot plug detect.

hdmi_tx_i2c_sda

Input/Output

1

HDMI I2C SDA for DDC and SCDC.

hdmi_tx_i2c_scl

Input/Output

1

HDMI I2C SCL for DDC and SCDC.

hdmi_tx_ti_i2c_sda

Input/Output

1

HDMI I2C SDA for redriver control.

hdmi_tx_ti_i2c_scl

Input/Output

1

HDMI I2C SCL for redriver control.

phy_refclk0_p

Input

1

HDMI RX TMDS clock.

i_pma_cu_clk

input

1

Reset sequencer control signals

i_src_rs_grant

input

4

o_src_rs_req

Output

4

systempll_clk

input

1

Systempll clk

systempll_lock

input

1

Systempll lock signal

hdmi_rx_inst0_auto_phy_refclk0_n

input

1

RX Transceiver refclock

hdmi_rx_inst0_auto_phy_refclk0_p

input

1

hdmi_rx_inst0_auto_rx_serial_data

input

3

hdmi_rx_inst0_auto_rx_serial_data_n

input

3

hdmi_rx_inst0_auto_rx_ready

Output

1

Indicates that the transceiver is ready

hdmi_rx_inst0_auto_audio_CTS

Output

20

HDMI RX core audio interfaces.

For more information, refer to "Sink Interfaces" in GTS HDMI Intel® FPGA IP User Guide .

hdmi_rx_inst0_auto_audio_N

Output

20

hdmi_rx_inst0_auto_audio_data

Output

256

hdmi_rx_inst0_auto_audio_de

Output

1

hdmi_rx_inst0_auto_audio_format

Output

5

hdmi_rx_inst0_auto_audio_info_ai

Output

48

hdmi_rx_inst0_auto_audio_metadata

Output

165

hdmi_rx_inst0_auto_aux_data

Output

72

HDMI RX core auxiliary interfaces.

For more information, refer to "Sink Interfaces" in GTS HDMI Intel® FPGA IP User Guide .

hdmi_rx_inst0_auto_aux_eop

Output

1

hdmi_rx_inst0_auto_aux_error

Output

1

hdmi_rx_inst0_auto_aux_pkt_addr

Output

7

hdmi_rx_inst0_auto_aux_pkt_data

Output

72

hdmi_rx_inst0_auto_aux_pkt_wr

Output

1

hdmi_rx_inst0_auto_aux_sop

Output

1

hdmi_rx_inst0_auto_aux_valid

Output

1

hdmi_rx_inst0_auto_ctrl

Output

12

HDMI RX core control and status ports.

Note: N = symbols per clock

hdmi_rx_inst0_auto_mode

Output

1

hdmi_rx_inst0_auto_edid_ram_access

input

1

HDMI RX EDID RAM access interface.

Assert edid_ram_access when you want to write or read from the EDID RAM, else this signal should be kept low.

When you assert edid_ram_access, the hotplug signal deasserts to allow write or read to the EDID RAM. When EDID RAM access is completed, you should deassert edid_ram_assess and the hotplug signal asserts. The source reads the new EDID due to the hotplug signal toggling.

hdmi_rx_inst0_auto_edid_ram_address

input

8

hdmi_rx_inst0_auto_edid_ram_read

input

1

hdmi_rx_inst0_auto_edid_ram_readdata

Output

8

hdmi_rx_inst0_auto_edid_ram_waitrequest

Output

1

hdmi_rx_inst0_auto_edid_ram_write

input

1

hdmi_rx_inst0_auto_edid_ram_writedata

input

8

hdmi_rx_inst0_auto_i2c_scl

input

1

HDMI RX DDC and SCDC interface.

hdmi_rx_inst0_auto_i2c_sda

inout

1

hdmi_rx_inst0_auto_tmds_config_trans_det

Output

1

For more information, refer to "Sink Interfaces" in GTS HDMI Intel® FPGA IP User Guide .

hdmi_rx_inst0_auto_i2c_clk

input

1

I2C Clock

hdmi_rx_inst0_auto_rx_hpd_req

Output

1

HDMI RX 5V detect and hotplug detect.

For more information, refer to "Sink Interfaces" in GTS HDMI Intel® FPGA IP User Guide .

hdmi_rx_inst0_auto_in_5v_power

input

1

hdmi_rx_inst0_auto_info_avi

Output

123

HDMI RX core sideband signals.

For more information, refer to "Sink Interfaces" in GTS HDMI Intel® FPGA IP User Guide .

hdmi_rx_inst0_auto_info_vsi

Output

61

hdmi_rx_inst0_auto_gcp

Output

6

hdmi_rx_inst0_auto_reset

input

1

Reset signal

hdmi_rx_inst0_auto_scrambler_enable

Output

1

Indicates if the received data is scrambled; corresponds to the Scrambling_Enable field in the SCDC register 0x20 bit 0.

hdmi_rx_inst0_auto_tmds_bit_clock_ratio

Output

1

hdmi_rx_inst0_auto_vid_clk

input

1

Video Clock

hdmi_rx_inst0_auto_locked

Output

1

HDMI RX core video ports.

Note: N = pixels per clock

For more information, refer to "Sink Interfaces" in GTS HDMI Intel® FPGA IP User Guide .

hdmi_rx_inst0_auto_os

input

1

hdmi_rx_inst0_auto_vid_data

Output

96

hdmi_rx_inst0_auto_vid_de

Output

2

hdmi_rx_inst0_auto_vid_hsync

Output

2

hdmi_rx_inst0_auto_vid_lock

Output

1

hdmi_rx_inst0_auto_vid_valid

Output

1

hdmi_rx_inst0_auto_vid_vsync

Output

2

hdmi_tx_inst0_auto_phy_refclk0_n

input

1

TX Transceiver refclock

hdmi_tx_inst0_auto_phy_refclk0_p

input

1

hdmi_tx_inst0_auto_tx_serial_data

Output

4

TX Transceiver serial data

hdmi_tx_inst0_auto_tx_serial_data_n

Output

4

hdmi_tx_inst0_auto_tx_ready

Output

1

Indicate transceiver is ready

hdmi_tx_inst0_auto_audio_CTS

input

20

HDMI TX core audio interfaces.

For more information, refer to "Source Interfaces" in GTS HDMI Intel® FPGA IP User Guide .

hdmi_tx_inst0_auto_audio_N

input

20

hdmi_tx_inst0_auto_audio_clk

input

1

hdmi_tx_inst0_auto_audio_data

input

256

hdmi_tx_inst0_auto_audio_de

input

1

hdmi_tx_inst0_auto_audio_format

input

5

hdmi_tx_inst0_auto_audio_info_ai

input

49

hdmi_tx_inst0_auto_audio_metadata

input

166

hdmi_tx_inst0_auto_audio_mute

input

1

hdmi_tx_inst0_auto_aux_data

input

72

HDMI TX core auxiliary interfaces.

For more information, refer to "Source Interfaces" in GTS HDMI Intel® FPGA IP User Guide .

hdmi_tx_inst0_auto_aux_eop

input

1

hdmi_tx_inst0_auto_aux_ready

Output

1

hdmi_tx_inst0_auto_aux_sop

input

1

hdmi_tx_inst0_auto_aux_valid

input

1

hdmi_tx_inst0_auto_gcp

input

6

HDMI TX core sideband signals.

For more information, refer to "Source Interfaces" in GTS HDMI Intel® FPGA IP User Guide .

hdmi_tx_inst0_auto_info_avi

input

123

hdmi_tx_inst0_auto_info_vsi

input

62

hdmi_tx_inst0_auto_mode

input

1

HDMI TX core control interfaces.

Note: N = pixels per clock

For more information, refer to "Source Interfaces" in GTS HDMI Intel® FPGA IP User Guide .

hdmi_tx_inst0_auto_ctrl

input

12

hdmi_tx_inst0_auto_i2c_master_address

input

4

TX I2C master Avalon memory-mapped interface to I2C master inside the TX core.

Note: These signals are available only when you turn on the Include I2C parameter.

hdmi_tx_inst0_auto_i2c_master_read

input

1

hdmi_tx_inst0_auto_i2c_master_readdata

Output

32

hdmi_tx_inst0_auto_i2c_master_write

input

1

hdmi_tx_inst0_auto_i2c_master_writedata

input

32

hdmi_tx_inst0_auto_i2c_scl

inout

1

I2c Signals

hdmi_tx_inst0_auto_i2c_sda

inout

1

hdmi_tx_inst0_auto_mgmt_clk

input

1

100mhz clock

hdmi_tx_inst0_auto_os

input

2

Oversample input signal

hdmi_tx_inst0_auto_reset

input

1

Reset signals

hdmi_tx_inst0_auto_scrambler_enable

input

1

Indicates if the data is scrambled.

hdmi_tx_inst0_auto_tmds_bit_clock_ratio

input

1

hdmi_tx_inst0_auto_tx_hpd

input

1

HDMI TX hotplug detect interfaces.

hdmi_tx_inst0_auto_tx_hpd_req

Output

1

hdmi_tx_inst0_auto_vid_clk

input

1

Video Clock

hdmi_tx_inst0_auto_vid_data

input

96

HDMI TX core video ports.

Note: N = pixels per clock

For more information, refer to "Source Interfaces" in GTS HDMI Intel® FPGA IP User Guide .

hdmi_tx_inst0_auto_vid_de

input

2

hdmi_tx_inst0_auto_vid_hsync

input

2

hdmi_tx_inst0_auto_vid_overflow

Output

1

hdmi_tx_inst0_auto_vid_ready

Output

1

hdmi_tx_inst0_auto_vid_valid

input

1

hdmi_tx_inst0_auto_vid_vsync

input

2

reset

Input

1

System reset input.

mgmt_clk

Input

1

System clock input (100 MHz).

pll_pixel_refclk

Input

1

Video Actual Pixel clock.

vid_clk

Input

1

HDMI video clock.

rx_vid_lock

Input

3

Indicates HDMI RX video lock status.

rx_vid_valid

Input

1

HDMI RX video interfaces.

rx_vid_de

Input

N

rx_vid_hsync

Input

N

rx_vid_vsync

Input

N

rx_vid_data

Input

N*48

rx_aux_eop

Input

1

HDMI RX auxiliary interfaces.

rx_aux_sop

Input

1

rx_aux_valid

Input

1

rx_aux_data

Input

72

tx_vid_de

Output

N

HDMI TX video interfaces.

Note: N = pixels per clock.

tx_vid_hsync

Output

N

tx_vid_vsync

Output

N

tx_vid_data

Output

N*48

tx_vid_valid

Output

1

tx_vid_ready

Input

1

tx_aux_eop

Output

1

HDMI TX auxiliary interfaces.

tx_aux_sop

Output

1

tx_aux_valid

Output

1

tx_aux_data

Output

72

tx_aux_ready

Input

1

cpu_clk_in_clk_clk

Input

1

CPU clock.

cpu_rst_in_reset_reset

Input

1

CPU reset.

edid_ram_slave_translator_avalon_anti_slave

_0_address

Output

8

EDID RAM access interfaces.

edid_ram_slave_translator_avalon_anti_slave

_0_write

Output

1

edid_ram_slave_translator_avalon_anti_slave

_0_read

Output

1

edid_ram_slave_translator_avalon_anti_slave

_0_readdata

Input

8

edid_ram_slave_translator_avalon_anti_slave

_0_writedata

Output

8

edid_ram_slave_translator_avalon_anti_slave

_0_waitrequest

Input

1

hdmi_i2c_master_i2c_serial_sda_in

Input

1

I2C Master interfaces from the Nios II processor to the output buffer for DDC and SCDC control.

hdmi_i2c_master_i2c_serial_scl_in

Input

1

hdmi_i2c_master_i2c_serial_sda_oe

Output

1

hdmi_i2c_master_i2c_serial_scl_oe

Output

1

redriver_i2c_master_i2c_serial_sda_in

Input

1

I2C Master interfaces from the Nios II processor to the output buffer for TI redriver setting configuration.

redriver_i2c_master_i2c_serial_scl_in

Input

1

redriver_i2c_master_i2c_serial_sda_oe

Output

1

redriver_i2c_master_i2c_serial_scl_oe

Output

1

pio_in0_external_connection_export

Input

32

Parallel input output interfaces.

Bit 0: Connected to the user_dipsw signal to control EDID passthrough mode

Bit 1: TX HPD request

Bit 2: TX transceiver ready

Bits 3: TX reconfiguration done

Bits 4–7: Reserved

Bits 8–11: RX FRL rate

Bit 12: RX TMDS bit clock ratio

Bits 13–16: RX FRL

locked

Bits 17–20: RX FFE

levels

Bit 21: RX alignment locked

Bit 22: RX video lock

Bit 23: User push button 2 to read SCDC registers from external sink

Bits 24–31: Reserved

pio_out0_external_connection_export

Output

32

Parallel input output interfaces.

Bit 0: TX HPD

acknowledgment

Bit 1: TX initialization is done

Bits 2–7: Reserved

Bits 8–11: TX FRL rate

Bits 12–27: TX FRL link training pattern

Bit 28: TX FRL start

Bits 29–31: Reserved

pio_out1_external_connection_export

Output

32

Parallel input output interfaces.

Bit 0: RX EDID RAM

access

Bit 1: RX FLT ready

Bits 2–7: Reserved

Bits 8–15: RX FRL

source test configuration

Bits 16–31: Reserved