GTS Transceiver Dual Simplex Interfaces User Guide

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ID 825853
Date 10/07/2024
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Overview 3. Understanding and Planning Dual Simplex Interfaces 4. Implementing Dual Simplex Interfaces 5. Document Revision History for the GTS Transceiver Dual Simplex Interfaces User Guide
4. Implementing Dual Simplex Interfaces x
4.1. Generating the Simplex IP 4.2. Using the Dual Simplex Assignment Editor 4.3. Generating the Dual Simplex IP 4.4. Connecting the Dual Simplex IP 4.5. Verifying the Dual Simplex IP Implementation
1. Introduction
2. Overview
3. Understanding and Planning Dual Simplex Interfaces
4. Implementing Dual Simplex Interfaces
5. Document Revision History for the GTS Transceiver Dual Simplex Interfaces User Guide

1. Introduction

Updated for:
Intel® Quartus® Prime Design Suite 24.3
This user guide describes the method to implement the dual simplex (DS) mode in Agilex™ 5 GTS transceivers.
The dual simplex mode refers to the operating mode of the GTS transceiver channel where you can place an independent transmitter and an independent receiver in the same transceiver channel, thereby maximizing the transceiver resource utilization in Agilex™ 5 FPGAs. The user guide describes:
  • Supported simplex protocol IPs in dual simplex mode
  • How to plan for dual simplex interfaces prior to starting your design
  • How to implement the dual simplex design flow

You can implement the dual simplex mode in Quartus® Prime Pro Edition software version 24.2 onwards.

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