Device Migration Guidelines: Agilex™ 5 FPGAs and SoCs E-Series

ID 813955
Date 7/26/2024
Public
Document Table of Contents

3.7.3.7. System PLL in Downbonded Quads

Take note of the System PLL resource count in the device that you select and the device you plan to migrate to, that consist of the downbonded GTS transceiver bank.

Each downbonded GTS transceiver bank contains one System PLL that can be fed to the FPGA Core. Refer to the GTS Transceiver PHY User Guide for more information.