Device Migration Guidelines: Agilex™ 5 FPGAs and SoCs E-Series

ID 813955
Date 7/26/2024
Public
Document Table of Contents

3.4.1. External Memory Protocol Supported in Agilex™ 5 E-Series Devices

Agilex™ 5 E-Series devices for Device Group A support DDR4, DDR5, LPDDR4, and LPDDR5 protocols while devices for Device Group B support DDR4, LPDDR4, and LPDDR5 protocols. All Agilex™ 5 E-Series devices only support component memory type.

Refer to the Agilex™ 5 FPGAs and SoCs Device Data Sheet for details of supported protocol in Device Group A and B.

The maximum number of External Memory Interface for each device depends on the number of HSIO banks and HSIO pin counts available in the device.

Refer to Package Options, Migrations, and I/O Pins for HSIO count availability for each device.
4
  • HSIO – High-speed I/O
  • HVIO – High voltage I/O
  • LVDS – Low voltage differential signaling channels